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e 1/22/98 1:50 pm 24333502.doc intel confidential (until publication date) information in this document is provided solely to enable use of intel products. intel assumes no liab ility whatsoever, including infri ngement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for s uch products. information contained herein supersedes previousl y published specifications on these devices from intel. ? intel corporation 1995 januar y 1998 order number: 243335-003 n available at 233 mhz, 266 mhz, 300 mhz, and 333 mhz core frequencies n binary compatible with applications running on previous members of the intel microprocessor line n dynamic execution micro architecture n dual independent bus architecture: separate dedicated external system bus and dedicated internal high-speed cache bus n intels highest performance processor combines the power of the pentium ? pro processor with the capabilities of mmx? technology n power management capabilities ? system management mode ? multiple low-power states n optimized for 32-bit applications running on advanced 32-bit operating systems n single edge contact (s.e.c.) cartridge packaging technology; the s.e.c. cartridge delivers high performance with improved handling protection and socketability n integrated high performance 16 kb instruction and 16 kb data, nonblocking, level one cache n available with integrated 512 kb unified, nonblocking, level two cache n enables systems which are scaleable up to two processors and 64 gb of physical memory n error-correcting code for system bus data the intel pentium ? ii processor is designed for high-performance desktops, workstations and mainstream servers, and is binary compatible with previous intel architecture processors. the pentium ii processor provides the best performance available for applications running on advanced operating systems such as w indows* 95, windows nt and unix*. this is achieved by integrating the best attributes of intels processors the dynamic execution performance of the pentium pro processor plus the capabilities of mmx? technology bringing a new level of performance for system buyers. the pentium ii processor is sc aleable to two processors in a multiprocessor system and extends the power of the pentium pro processor with performance headroom for business media, communication and internet capabilities. systems based on pentium ii processors also include the latest features to simplify system m anagement and lower the cost of ownership for large and small business environments. pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 2 intel secret (until publication date) information in this document is provided in connection with intel products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantabili ty, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arisi ng from future changes to them. the pentium ? ii processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request.contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtained from by calling 1-800-548-4725 or by visiting intels website at http://www.intel.com. copyright ? intel corporation 1996, 1997. * third-party brands and names are the property of their respective owners.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 3 intel secret (until publication date) contents page page 1.0. introduction ............................................... 7 1.1. terminology.................................................... 8 1.1.1. s.e.c. cartridge terminology ... 8 1.2. references..................................................... 8 2.0. electrical specifications .................... 9 2.1. the pentium ? ii processor system bus and v ref ............................................................. 9 2.2. clock control and low power states ............ 9 2.2.1. normal state state 1.............. 10 2.2.2. auto halt power down state state 2 ............................................... 10 2.2.3. stop-grant state state 3 ..... 11 2.2.4. halt/grant snoop state state 4 ............................................... 11 2.2.5. sleep state state 5 ................. 11 2.2.6. deep sleep state state 6 ...... 12 2.2.7. clock control and low power modes................................................. 12 2.3. power and ground pins............................... 12 2.4. decoupling guidelines ................................. 12 2.4.1. system bus gtl+ decoupling ... 13 2.5. pentium ? ii processor system bus clock and processor clocking............................... 13 2.5.1. mixing processors of different frequencies.............. 16 2.6. voltage identification .................................... 16 2.7. pentium ? ii processor system bus unused pins .............................................................. 18 2.8. pentium ? ii processor system bus signal groups ......................................................... 18 2.8.1. asynchronous vs. synchronous for system bus signals .............................................. 20 2.9. test access port (tap) connection............ 20 2.10. maximum ratings ...................................... 20 2.11. processor dc specifications ..................... 20 2.12. gtl+ system bus specifications .............. 26 2.13. pentium ? ii processor system bus ac specifications............................................... 26 3.0. system bus signal simulations......... 37 3.1. system bus clock (bclk) signal quality specifications............................................... 37 3.2. gtl+ signal quality specifications.............. 39 3.3. non-gtl+ signal quality specifications...... 39 3.3.1. overshoot/undershoot guidelines........................................ 39 3.3.2. ringback specification .............. 41 3.3.3. settling limit guideline.............. 41 4.0. thermal specifications and design considerations........................................ 42 4.1. thermal specifications................................. 42 4.2. pentium ? ii processor thermal analysis ... 43 4.2.1. thermal solution performance.................................. 43 4.2.2. measurements for thermal specifications................................ 44 4.2.2.1. thermal plate temperature measurement ................................. 44 4.2.2.2. cover temperature measurement . 45 4.3. thermal solution attach methods ................ 45 4.3.1. heatsink clip attach ................... 45 4.3.2. rivscrew* attach.......................... 47 5.0. s.e.c. cartridge mechanical specifications .......................................... 51 5.1. s.e.c. cartridge materials information ........ 51 5.2. processor edge finger signal listing.......... 63 6.0. boxed processor specifications .... 73 6.1. introduction................................................... 73 6.2. mechanical specifications............................ 74 6.2.1. boxed processor fan/heatsink dimensions....................................... 74 6.2.2. boxed processor fan/heatsink weight.................... 76 6.2.3. boxed processor retention mechanism and fan/heatsink support ............................................ 76 6.3. boxed processor requirements .................. 79 6.3.1. fan/heatsink power supply...... 79
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 4 intel secret (until publication date) 6.4. thermal specifications................................. 81 6.4.1. boxed processor cooling requirements ................................ 81 7.0. advanced features................................ 82 a.1 alphabetical signals reference .... 83 a.1.1 a[35:0]# (i/o) ......................................... 83 a.1.2 a20m# (i) ............................................... 83 a.1.3 ads# (i/o) ............................................. 83 a.1.4 aerr# (i/o) .......................................... 83 a.1.5 ap[1:0]# (i/o)......................................... 83 a.1.6 bclk (i) ................................................. 84 a.1.7 berr# (i/o) .......................................... 84 a.1.8 binit# (i/o) ........................................... 84 a.1.9 bnr# (i/o)............................................. 84 a.1.10 bp[3:2]# (i/o)....................................... 84 a.1.11 bpm[1:0]# (i/o).................................... 84 a.1.12 bpri# (i) .............................................. 84 a.1.13 br0# (i/o), br1# (i) ............................ 85 a.1.14 bsel# (i/o) ......................................... 85 a.1.15 d[63:0]# (i/o) ....................................... 85 a.1.16 dbsy# (i/o)......................................... 85 a.1.17 defer# (i) .......................................... 85 a.1.18 dep[7:0]# (i/o) .................................... 85 a.1.19 drdy# (i/o) ........................................ 85 a.1.20 emi....................................................... 86 a.1.21 ferr# (o)........................................... 86 a.1.22 flush# (i)........................................... 86 a.1.23 frcerr (i/o) ..................................... 86 a.1.24 hit# (i/o), hitm# (i/o)........................ 86 a.1.25 ierr# (o)............................................ 86 a.1.26 ignne# (i)........................................... 87 a.1.27 init# (i)................................................ 87 a.1.28 lint[1:0] (i).......................................... 87 a.1.29 lock# (i/o)......................................... 87 a.1.30 picclk (i) ........................................... 87 a.1.31 picd[1:0] (i/o)..................................... 88 a.1.32 pm[1:0]# (o) ........................................ 88 a.1.33 prdy# (o) .......................................... 88 a.1.34 preq# (i) ............................................ 88 a.1.35 pwrgood (i)..................................... 88 a.1.36 req[4:0]# (i/o).................................... 88 a.1.37 reset# (i) .......................................... 88 a.1.38 rp# (i/o).............................................. 89 a.1.39 rs[2:0]# (i)........................................... 89 a.1.40 rsp# (i) ............................................... 89 a.1.41 slotocc# (o) ................................... 89 a.1.42 slp# (i)................................................ 90 a.1.43 smi# (i) ................................................ 90 a.1.44 stpclk# (i) ........................................ 90 a.1.454 tck (i) ............................................... 90 a.1.46 tdi (i)................................................... 90 a.1.47 tdo (o) ............................................... 90 a.1.48 testhi (i)............................................ 90 a.1.49 thermtrip# (o) ............................... 90 a.1.50 tms (i) ................................................. 90 a.1.51 trdy# (i)............................................. 90 a.1.52 trst# (i) ............................................. 90 a.1.53 vid[4:0] (o).......................................... 91 a.2 signal summaries..................................... 91 figures figure 1. second level (l2) cache implementations.................................... 7 figure 2. gtl+ bus topology............................... 9 figure 3. stop clock state machine.................... 10 figure 4. timing diagram of system bus multiplier signals................................. 14 figure 5. example schematic for system bus multiplier pin sharing .......................... 15 figure 6. bclk to core logic offset .................. 32 figure 7. bclk, tck, picclk generic clock wave form ......................................... 32 figure 8. system bus valid delay timings......... 33 figure 9. system bus setup and hold timings .. 33 figure 10. frc mode bclk to picclk timing . 34 figure 11. system bus reset and configuration timings ............................................... 34 figure 12. power-on reset and configuration timings ............................................... 35 figure 13. test timings (tap connection)......... 36 figure 14. test reset timings ............................ 36 figure 15. bclk, tck, picclk generic clock wave form at the processor edge fingers ................................................ 37
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 5 intel secret (until publication date) figure 16. low to high gtl+ receiver ringback tolerance............................................ 38 figure 17. non-gtl+ overshoot/undershoot and ringback............................................. 40 figure 18. processor s.e.c. cartridge thermal plate.................................................... 42 figure 19. processor thermal plate temperature measurement location ....................... 44 figure 20. technique for measuring t plate with 0 angle attachment ........................... 45 figure 21. technique for measuring t plate with 90 angle attachment ......................... 45 figure 22. guideline locations for cover temperature (t cover ) thermocouple placement................... 46 figure 23. processor with an example low profile heatsink attached using spring clips.................................................... 46 figure 24. processor with an example full height heatsink attached using spring clips.................................................... 47 figure 25. heatsink recommendations and guidelines for use with rivscrews* ... 48 figure 26. heatsink rivscrew* and thermal plate recommendations and guidelines..... 48 figure 27. general rivscrew* heatsink mechanical recommendations .......... 49 figure 28. heatsink attachment mechanism design space ..................................... 50 figure 29. s.e.c. cartridge C thermal plate and cover side views ............................... 52 figure 30. s.e.c. cartridge overall cartridge dimensions ......................................... 53 figure 32. s.e.c. cartridge thermal plate and side view dimensions........................ 55 figure 33. s.e.c. cartridge thermal plate flatness dimensions .......................... 56 figure 34. s.e.c. cartridge latch details........... 57 figure 35. s.e.c. cartridge latch arm, thermal plate lug, and cover lug dimensions ......................................... 58 figure 36. s.e.c. cartridge mark locations ....... 59 figure 37. s.e.c. cartridge bottom side view ... 60 figure 38. s.e.c. cartridge substrate dimensions ......................................... 61 figure 39. s.e.c. cartridge substrate dimensions, cover side view ............ 61 figure 40. substrate C s.e.c. cartridge substrate detail a ............................................... 62 figure 41. conceptual boxed pentium ? ii processor in retention mechanism.... 73 figure 42. side view space requirements for the boxed processor (fan heatsink supports not shown) ........................... 74 figure 43. front view space requirements for the boxed processor .......................... 75 figure 44. top view space requirements for the boxed processor ................................ 75 figure 45. heatsink support hole locations and sizes ................................................... 77 figure 46. side view space requirements for boxed processor fan/heatsink supports.............................................. 78 figure 47. top view space requirements for boxed processor fan/heatsink supports.............................................. 79 figure 48. boxed processor fan/heatsink power cable connector description.............. 80 figure 49. recommended motherboard power header placement relative to fan power connector and slot 1............... 81 figure 50. pwrgood relationship at power-on............................................ 89 tables table 1. core frequency to system bus multiplier configuration ........................ 14 table 2. voltage identification definition ............. 17 table 3. recommended pull-up resistor values (approximate) for cmos signals ................................................. 18 table 4. pentium ? ii processor/slot 1 system bus signal groups............................... 19 table 5. pentium ? ii processor absolute maximum ratings ................................ 21 table 6. pentium ? ii processor voltage and current specifications.......................... 22 table 7. gtl+ signal groups dc specifications....................................... 25 table 8. non-gtl+ signal groups dc specifications....................................... 25 table 9. pentium ? ii processor gtl+ bus specifications....................................... 26
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 6 intel secret (until publication date) table 10. system bus ac specifications (clock) ................................................. 27 table 11. valid slot 1 system bus, core frequency and cache bus frequencies ......................................... 28 table 12. gtl+ signal groups system bus ac specifications....................................... 28 table 13. system bus ac specifications (cmos signal group)....................................... 29 table 14. system bus ac specifications (reset conditions)........................................... 29 table 15. system bus ac specifications (apic clock and apic i/o) ............................ 30 table 16. system bus ac specifications (tap connection).......................................... 31 table 17. bclk signal quality specifications .... 37 table 18. gtl+ signal groups ringback tolerance ............................................. 38 table 19. signal ringback specifications for non- gtl+ signals ....................................... 41 table 20. pentium ? ii processor thermal design specification......................................... 43 table 21. example thermal solution performance for 266 mhz pentium ? ii processor at thermal plate power of 37.0 watts............................................ 43 table 22. s.e.c. cartridge materials .................. 51 table 23. s.e.c. cartridge dimensions .............. 51 table 24. description table for processor markings .............................................. 59 table 25. signal listing in order by pin number ................................................ 63 table 26. signal listing in order by signal name.................................................... 68 table 27. boxed processor fan/heatsink spatial dimensions .......................................... 75 table 28. boxed processor fan/heatsink support dimensions............................. 76 table 29. fan/heatsink power and signal specifications....................................... 80 table 30. br0# (i/o) and br1# signals rotating interconnect ......................................... 85 table 31. br[1:0]# signal agent ids .................. 85 table 32. slot 1 occupation truth table ............ 89 table 33. output signals..................................... 91 table 34. input signals........................................ 92 table 35. input/output signals (single driver).... 93 table 36. input/output signals (multiple driver) . 93
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 7 intel secret (until publication date) 1.0. introduction the pentium ii processor is the next in the intel386?, intel486?, pentium and pentium pro line of intel processors. the pentium ii processor, like the pentium pro processor, implements a dynamic execution micro-architecture a unique combination of multiple branch prediction, data flow analysis and speculative execution. this enables the pentium ii processor to deliver higher performance than the pentium processor, while maintaining binary compatibility with all previous intel architecture processors. the pentium ii processor also executes mmx technology instructions for enhanced media and communication performance. the pentium ii processor utilizes multiple low-power states such as autohalt, stop- grant, sleep and deep sleep to conserve power during idle times. the pentium ii processor utilizes the same multi- processing system bus technology as the pentium pro processor. this allows for a higher level of performance for both uni-processor and two-way multi-processor (2-way mp) systems. memory is cacheable for up to 512 mb of addressable memory space, allowing significant headroom for business desktop systems. the pentium ii processor system bus operates in the same manner as the pentium pro processor system bus. the pentium ii processor system bus uses gtl+ signal technology. the pentium ii processor deviates from the pentium pro processor by using commercially available die for the l2 cache. the l2 cache (the tagram and burst pipeline synchronous static ram (bsram) memories) are now multiple die. transfer rates between the pentium ii processor core and the l2 cache are one-half the processor core clock frequency and scale with the processor core frequency. both the tagram and bsram receive clocked data directly from the pentium ii processor core. as with the pentium pro processor, the l2 cache does not connect to the pentium ii processor system bus (see figure 1). as with the pentium pro processor, the pentium ii processor has a dedicated l2 bus, thus maintaining the dual independent bus architecture to deliver high bus bandwidth and high performance (see figure 1). the pentium ii processor utilizes single edge contact (s.e.c.) cartridge packaging technology. the s.e.c. cartridge allows the l2 cache to remain tightly coupled to the processor, while enabling use of high volume commercial sram components. the l2 cache is performance optimized and tested at the package level. the s.e.c. cartridge utilizes surface mount technology and a substrate with an edge finger connection. the s.e.c. cartridge introduced on the pentium ii processor will also be used in future slot 1 processors. the s.e.c. cartridge has the following features: a thermal plate, a cover and a substrate with an edge finger connection. the thermal plate allows standardized heatsink attachment or customized thermal solutions. the full enclosure also protects the surface mount components. the edge finger connection maintains socketability for system configuration. the edge finger connector is noted as slot 1 connector in this and other documentation. pentium ii processor substrate and components processor core processor core tag l2 pentium ? pro processor dual die cavity package l2 schematic only 000756c figure 1. second level (l2) cache implementations
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 8 intel secret (until publication date) 1.1. terminology in this document, a # symbol after a signal name refers to an active low signal. this means that a signal is in the active state (based on the name of the signal) when driven to a low level. for example, when flush# is low, a flush has been requested. when nmi is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data ), the # symbol implies that the signal is inverted. for example, d[3:0] = hlhl refers to a hex a, and d#[3:0] = lhlh also refers to a hex a (h= high logic level, l= low logic level). the term system bus refers to the interface between the processor, system core logic (a.k.a. the pciset components) and other bus agents. the system bus is a multiprocessing interface to processors, memory and i/o. the term cache bus refers to the interface between the processor and the l2 cache components (tagram and bsrams). the cache bus does not connect to the system bus, and is not visible to other agents on the system bus. 1.1.1. s.e.c. cartridge terminology the following terms are used often in this document and are explained here for clarification: pentium ? ii processor the entire product including internal components, substrate, thermal plate and cover. s.e.c. cartridge the new processor packaging technology is called a single edge contact cartridge. processor substrate the structure on which the components are mounted inside the s.e.c. cartridge (with or without components attached). processor core the processors execution engine. thermal plate the surface used to connect a heatsink or other thermal solutions to the processor. cover the processor casing on the opposite side of the thermal plate. latch arms a processor feature that can be utilized as a means for securing the processor in the retention mechanism. additional terms referred to in this and other related documentation: slot 1 the connector that the s.e.c. cartridge plugs into, just as the pentium ? pro processor uses socket 8. retention mechanism an enabled mechanical piece which holds the package in the slot 1 connector. heatsink support the support pieces that are mounted on the motherboard to provide added support for heatsinks. the l2 cache (tagram, bsram) dies keep standard industry names. 1.2. references the reader of this specification should also be familiar with material and concepts presented in the following documents: ap-485, intel processor identification with the cpuid instruction (order number 241618) ap-585, pentium ? ii processor gtl+ guidelines (order number 243330) ap-586, pentium ? ii processor thermal design guidelines (order number 243333) ap-587, pentium ? ii processor power distribution guidelines (order number 243332) ap-588, mechanical and assembly technology for s.e.c. cartridge processors (order number 243333) ap-589, pentium ? ii processor electro-magnetic interference (order number 243334) pentium ? ii processor specification update (order number 243337) pentium ? ii processor i/o buffer models, ibis format (electronic form) pentium ? ii processor developers manual (order number 243341) intel architecture software developers manual volume i: basic architecture (order number 243190) volume ii: instruction set reference (order number 243191) volume iii: system programming guide (order number 243192)
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 9 intel secret (until publication date) 2.0. electrical specifications 2.1. the pentium ? ii processor system bus and v ref most of the pentium ii processor signals use a variation of the low voltage gunning transceiver logic (gtl) signaling technology. the pentium ii processor system bus specification is similar to the gtl specification, but has been enhanced to provide larger noise margins and reduced ringing. the improvements are accomplished by increasing the termination voltage level and controlling the edge rates. because this specification is different from the standard gtl specification, it is referred to as gtl+ in this document. for more information on gtl+ specifications, see ap-585, pentium ? ii processor gtl+ guidelines (order number 243330). the gtl+ signals are open-drain and requires termination to a supply that provides the high signal level. the gtl+ inputs use differential receivers which require a reference signal (v ref ). termination (usually a resistor at each end of the signal trace) is used to pull the bus up to the high voltage level and to control reflections on the transmission line. v ref is used by the receivers to determine if a signal is a logical 0 or a logical 1, and is generated on the s.e.c. cartridge for the processor core. the processor contains termination resistors that provide termination for one end of the pentium ii processor system bus. termination (usually a resistor on each end of the signal trace) is used to pull the bus up to the high voltage level and to control reflections on the transmission line. see table 9 for the bus termination voltage specifications for gtl+ and the pentium ? ii processor developers manual (order number 243341) for the gtl+ bus specification. v ref is generated on the s.e.c. cartridge for the pentium ii processor core. local v ref copies should be generated on the motherboard for all other devices on the gtl+ system bus. figure 2 is a schematic representation of gtl+ bus topology with the pentium ii processor. the gtl+ bus depends on incident wave switching. therefore timing calculations for gtl+ signals are based on flight time as opposed to capacitive deratings. analog signal simulation of the pentium ii processor system bus including trace lengths is highly recommended when designing a system with a heavily loaded gtl+ bus. see intels world wide web page (http:// www.intel.com) to downl oad the buffer models, pentium ? ii processor i/o buffer models, ibis format (electronic form). 2.2. clock control and low power states the pentium ii processor allows the use of autohalt, stop-grant, sleep and deep sleep states to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. see figure 3 for a visual representation of the pentium ii processor low power states. for the processor to fully realize the low current consumption of the stop-grant, sleep and deep sleep states, a model specific register (msr) bit must be set. for the msr at 02ah (hex), bit 26 must be set to a 1 (this is the power on default setting) for the processor to stop all internal clocks during these modes. for more information, see the pentium ? ii processor developers manual (order number 243341). pentium ? ii processor no stubs asic asic pentium ii processor 000916 figure 2. gtl+ bus topology
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 10 intel secret (until publication date) 2. auto halt power down state bclk running. snoops and interrupts allowed. halt instruction and halt bus cycle generated init#, binit#, intr, nmi, smi#, reset# 1. normal state normal execution. stpclk# asserted stpclk# de-asserted 3. stop grant state bclk running. snoops and interrupts allowed. slp# asserted slp# de-asserted 5. sleep state bclk running. no snoops or interrupts allowed. bclk input stopped bclk input restarted 6. deep sleep state bclk stopped. no snoops or interrupts allowed. 4. halt/grant snoop state bclk running. service snoops to caches. snoop event occurs snoop event serviced snoop event occurs snoop event serviced stpclk# asserted stpclk# de-asserted b757a figure 3. stop clock state machine due to the inability of processors to recognize bus transactions during sleep state and deep sleep state, two-way mp systems are not allowed to have one processor in sleep/deep sleep state and the other processor in normal or stop-grant states simultaneously. 2.2.1. normal state state 1 this is the normal operating state for the processor. 2.2.2. auto halt power down state state 2 autohalt is a low power state entered when the processor executes the halt instruction. the processor will transition to the normal state upon the occurrence of smi#, binit#, init#, or lint[1:0] (nmi, intr). reset# will cause the processor to immediately initialize itself. the return from the smi handler can be to either normal mode or the autohalt power down state. see the intel architecture software developers manual, volume iii: system programming guide (order number 243192) for more information.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 11 intel secret (until publication date) flush# will be serviced during autohalt state and the processor will return to the autohalt state. the system can generate a stpclk# while the processor is in the autohalt power down state. when the system deasserts the stpclk# interrupt, the processor will return execution to the halt state. 2.2.3. stop-grant state state 3 the stop-grant state on the processor is entered when the stpclk# signal is asserted. since the gtl+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to v tt ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the system bus should be driven to the inactive state. flush# will be serviced during stop-grant state and the processor will return to the stop-grant state. reset# will cause the processor to immediately initialize itself, but the processor will stay in stop- grant state. a transition back to the normal state will occur with the deassertion of the stpclk# signal. a transition to the halt/grant snoop state will occur when the processor detects a snoop on the system bus (see section 2.2.4.). a transition to the sleep state (see section 2.2.5.) will occur with the assertion of the slp# signal. while in the stop-grant state, smi#, init# and lint[1:0] will be latched by the processor, and only serviced when the processor returns to the normal state. only one occurrence of each event will be recognized upon return to the normal state. 2.2.4. halt/grant snoop state state 4 the processor will respond to snoop transactions on the slot 1 processor system bus while in stop-grant state or in autohalt power down state. during a snoop transaction, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the slot 1 processor system bus has been serviced (whether by the processor or another agent on the slot 1 by the processor or another agent on the slot 1 processor system bus). after the snoop is serviced, the processor will return to the stop-grant state or autohalt power down state, as appropriate. 2.2.5. sleep state state 5 the sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (pll), and has stopped all internal clocks. the sl eep state can only be entered from stop-grant state. once in the stop-grant state, the slp# pin can be asserted, causing the processor to enter the sleep state. the slp# pin is not recognized in the normal or autohalt states. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp# or reset#) are allowed on the system bus while the processor is in sl eep state. any transition on an input signal before the processor has returned to stop grant state will result in unpredictable behavior. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin specification, t hen the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immediately after r eset# is asserted to ensure the processor correctly executes the reset sequence. while in the sleep state, the processor is capable of entering its lowest power state, the deep sleep state, by stopping the bclk input. (see section 2.2.6.) once in the sleep or deep sleep states, the slp# pin can be deasserted if another asynchronous system bus event occurs. the slp# pin has a minimum assertion of one bclk period.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 12 intel secret (until publication date) 2.2.6. deep sleep state state 6 the deep sleep state is the lowest power state the processor can enter while maintaining context. the deep sleep state is entered by stopping the bclk input (after the sleep state was entered from the assertion of the slp# pin). the processor is in deep sleep state immediately after the bclk is stopped. it is recommended that the bclk input be held low during the deep sleep state. stopping of the bclk input lowers the overall current consumption to leakage levels. to re-enter the sleep state, the bclk input must be restarted. a period of 1 ms (to allow for pll stabilization) must occur before the processor can be considered to be in the sleep state. while in deep sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals are allowed on the system bus while the processor is in deep sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior. 2.2.7. clock control and low power modes the processor provides the clock signal to the l2 cache. during autohalt power down and stop- grant states, the processor will process the snoop phase of a system bus cycle. the processor w ill not stop the clock data to the l2 cache during autohalt power down or stop-grant states. entrance into the halt/grant snoop state will allow the l2 cache to be snooped, similar to normal state. when the processor is in sleep and deep sleep states, it will not respond to interrupts or snoop transactions. during sleep state, the clock to the l2 cache is not stopped. during the deep sleep state, the clock to the l2 cache is stopped. the clock to the l2 cache will be restarted only after the internal clocking mechanism for the processor is stable (i.e., the processor has re-entered sleep state). the picclk should not be removed during the autohalt power down or stop-grant states. the picclk can be removed during the sleep or deep sleep states. when transitioning from the deep sleep to sleep states, the picclk must be restarted with the bclk. 2.3. power and ground pins as future versions of pentium ii processors are released, the operating voltage of the processor core and of the l2 cache die may differ from each other. there are two groups of power inputs on the pentium ii processor package to support the possible voltage difference between the two components in the package. there are also five pins defined on the package for voltage identification (vid). these pins specify the voltage required by the processor core. these have been added to cleanly support voltage specification variations on current and future pentium ii processors. for clean on-chip power distribution, pentium ii processors have 27 v cc (power) and 30 v ss (ground) inputs. the 27 v cc pins are further divided to provide the different voltage levels to the components. vcc core inputs for the processor core and some l2 cache components account for 19 of the v cc pins, while 4 v tt inputs (1.5 v) are used to provide a gtl+ termination voltage to the processor and 3 vcc l2 inputs (3.3 v) are for use by the l2 cache tagram and bsrams. one vcc 5 pin is provided for use by the slot 1 test kit. vcc 5 , vcc l2 , and vcc core must remain electrically separated from each other. on the circuit board, all vcc core pins must be connected to a voltage island and all vcc l2 pins must be connected to a separate voltage island (an island is a portion of a power plane that has been divided, or an entire plane). similarly, all v ss pins must be connected to a system ground plane. 2.4. decoupling guidelines due to the large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. this causes voltages on power planes to sag below their nominal value if bulk decoupling is not adequate. care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in this document. failure to do so can result in timing violations or a reduced lifetime of the component.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 13 intel secret (until publication date) regulator solutions need to provide bulk capacitance with a low effective series resistance (esr) and keep an interconnect resistance from the regulator (or vrm pins) to the slot 1 connector of less than 0.5 m w . this can be accomplished by keeping a maximum distance of 1.5 inches between the regulator output and slot 1 connector. the recommended vcc core interconnect is a 2.0 inch wide (the width of the vrm connector) by 1.5 inch long (maximum distance between the slot 1 connector and the vrm connector) plane segment with a standard 1-ounce plating. bulk decoupling for the large current swings when the processor is powering on, or entering/exiting low power states, is provided on the voltage regulation module (vrm) defined in the pentium ? ii processor power distribution guidelines . the vcc core input should be capable of delivering a recommended minimum dicc core /dt (defined in table 6) while maintaining the tolerances (also defined in table 6). 2.4.1. system bus gtl+ decoupling the pentium ii processor contains high frequency decoupling capacitance on the processor substrate; however, bulk decoupling must be provided for by the system mother board for proper gtl+ bus operation. see ap-585, pentium ? ii processor gtl+ guidelines (order number 243330); ap-587, pentium ? ii processor power distribution guidelines (order number 243332); and pentium ? ii processor developers manual (order number 243341) for more information. 2.5. pentium ? ii processor system bus clock and processor clocking the bclk input directly controls the operating speed of the pentium ii processor system bus interface. all pentium ii processor system bus timing parameters are specified with respect to the rising edge of the bclk input. the pentium ii processor core frequency must be configured during reset by using the a20m#, ignne#, lint[1]/nmi and lint[0]/intr pins. (see table 1.) the value on these pins during reset determines the multiplier that the pll will use for the internal core clock. see the pentium ? ii processor developers manual (order number 243341) for the definition of these pins during reset and the operation of the pins after reset. see figure 4 for the timing relationship between the system bus multiplier signals, r eset#, creset# and normal processor operation. table 1 is a list of multipliers supported. all other multipliers are not authorized or supported. using creset# (cmos reset on the bas eboard), the circuit in figure 5 can be used to share these configuration signals. the component used as the multiplexer must not have outputs that drive higher than 2.5 v in order to meet the pentium ii processors 2.5 v tolerant buffer specifications. the multiplexer output current should be limited to 200 ma maximum, in case the vcc core supply to the processor ever fails. as shown in figure 4, the pull-up resistors between the multiplexer and the processor (330 w ) force a ratio of ? into the processor in the event that the pentium ii processor powers up before the multiplexer and/or the core logic. this prevents the processor from ever seeing a ratio higher than the final ratio. if the multiplexer were powered by vcc 2.5 , a pull- down could be used on creset# inst ead of the four pull-up resistors between the multiplexer and the pentium ii processor. in this case, the multiplexer must be designed such that the compatibility inputs are truly ignored, as their state is unknown. the compatibility inputs to the multiplexer must meet the input specifications of the multiplexer. this may require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already compatible. for frc mode operation, the multiplexer will need to be clocked using bclk to meet setup and hold times to the processors. this may require the use of high speed programmable logic. multiplying the bus clock frequency is required to increase performance while allowing for cost effective distribution of signals within a system. the system bus frequency multipliers supported are shown in table 11; other combinations will not be validated nor are they authorized for implementation .
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 14 intel secret (until publication date) table 1. core frequency to system bus multiplier configuration ratio of system bus to processor core frequency lint[1] lint[0] a20m# ignne# 1/2 l l l l 1/4 l l h l 1/5 l l h h 2/7 l h l h 2/9 l h h l 1/2 h h h h bclk reset# creset# system bus multiplier compatibility final ratio final ratio 000917a figure 4. timing diagram of system bus multiplier signals
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 15 intel secret (until publication date) a20m# ignne# lint1/nmi lint0/intr pentium ? ii processors 1k w 2.5 v set ratio: creset# mux 2.5 v 000918 figure 5. example schematic for system bus multiplier pin sharing
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 16 intel secret (until publication date) clock multiplying within the processor is provided by the internal phase lock loop (pll), requiring a constant frequency bclk input. the system bus frequency ratio cannot be changed dynamically during normal operation, nor can it be changed during any low power modes. the system bus frequency ratio can be changed when r eset# is active, assuming that all reset specifications are met. the bclk frequency should not be changed in deep sleep state. (see section 2.2.6.) 2.5.1. mixing processors of different frequencies mixing processor of different internal clock frequencies is not fully supported and has not been validated by intel. intel recommends using identical steppings of processor running at the same core/system frequencies. 2.6. voltage identification there are five voltage identification pins on the pentium ii processor/slot 1 connector. these pins can be used to support automatic selection of power supply voltages. these pins are not signals, but are either an open circuit or a short circuit to v ss on the processor. the combination of opens and shorts defines the voltage required by the processor core. the vid pins are needed to cleanly support voltage specification variations on the pentium ii and future processors. these pins (vid[0] through vid[4]) are defined in table 2. a 1 in this table refers to an open pin and a 0 refers to a short to ground. the definition provided below is a superset of the definition previously defined for the pentium pro processor. the power supply must supply the voltage that is requested or disable itself. table 2 provides the definition of vid[4:0]. to ensure the system is r eady for pentium ii processor variations, the range of values which are in bold in table 2 must be supported. a smaller range will risk the ability of the system to migrate to a hi gher performance processor. a wider range provides more flexibility and is acceptable. support for a wider range of vid settings will benefit the system in meeting the power requirements of future processors. note that the 11111 (all opens) id can be used to detect the absence of a processor core in a slot 1 connector as long as the power supply used does not affect these lines. detection logic and pull-ups should not affect vid inputs at the power source. (see section a.1.53.) the vid pins should be pulled up to a ttl- compatible level with external resistors to the power source of the regulator only if required by the regulator or external logic monitoring the vid[4:0] signals. the power source chosen must be guaranteed to be stable whenever the supply to the voltage regulator is stable. this will prevent the possibility of the processor supply going above 2.8 v in the event of a failure in the supply for the vid lines. in the case of a dc-to-dc converter, this can be accomplished by using the input voltage to the converter for the vid line pull-ups. a resistor of greater than or equal to 10k ohms should be used to connect the vid signals to the converter input. see the pentium ? ii processor power distribution guidelines for further information on power supply specifications for the pentium ii processor and future slot 1 processors.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 17 intel secret (until publication date) table 2. voltage identification definition 1, 2, 3 processor pins vid4 vid3 vid2 vid1 vid0 vcc core 0 1 1 1 1 reserved 0 1 1 1 0 reserved 0 1 1 0 1 reserved 0 1 1 0 0 reserved 0 1 0 1 1 reserved 0 1 0 1 0 reserved 0 1 0 0 1 reserved 0 1 0 0 0 reserved 0 0 1 1 1 reserved 0 0 1 1 0 reserved 00101 1.80 4 00100 1.85 4 00011 1.90 4 00010 1.95 4 00001 2.00 4 00000 2.05 4 11111 no core 11110 2.1 4 11101 2.2 4 11100 2.3 4 11011 2.4 4 11010 2.5 4 11001 2.6 4 11000 2.7 4 10111 2.8 4 10110 2.9 10101 3.0 10100 3.1 10011 3.2 10010 3.3 10001 3.4 10000 3.5 notes: 1. 0 = processor pin connected to v ss . 2. 1 = open on processor; may be pulled up to ttl v ih on motherboard. see the pentium? ii processor power distribution guidelines (order number 243332). 3. vrm output should be disabled for vcc core values less than 1.80 v. 4. to ensure the system is ready for pentium ? ii processor variations, the values in bold in table 2 must be supported.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 18 intel secret (until publication date) 2.7. pentium ? ii processor system bus unused pins all reserved pins must remain unc onnected. connection of reserved pins to vcc core , vcc l2 , v ss or to any signal can result in component malfunction or incompatibility with future slot 1 products. see section 5.2. for a pin listing of the processor and the location of each reserved pin. all testhi pins must be connected to 2.5 v via a pull-up resistor of between 1 and 10 k w value. picclk must be driven with a valid clock input and the picd[1:0] lines must be pulled-up to 2.5 v even when the local apic will not be used. a separate pull-up resistor must be provided for each picd line (see table 3 for recommended values). table 3. recommended pull-up resistor values (approximate) for cmos signals 1, 2, 3 recommended resistor value (approximate) cmos signal 150 tdo, tms, picd[0]#, picd[1]# 150 C 220 ferr#, ierr#, thermtrip# 150 C 330 a20m#, ignne#, init#, lint[1]/nmi, lint[0]/intr, pwrgood, slp#, preq#, tdi 410 stpclk#, smi# 500 flush# notes: 1. these resistor values are recommended for system implementations using open drain cmos buffers. 2. these approximate resistor values are for proper operation of debug tools only a ~150 w pull-up resistor is expected for these signals. 3. the trst# signal must be driven low at power on reset. this can be accomplished with a 680 w pull- down resistor. for reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. unused gtl+ inputs should be left as no connects; gtl+ termination is provided on the processor. unused active low cmos inputs should be connected to 2.5v. unused active high inputs should be connected to ground (v ss ). unused outputs can be left unconnected. a resistor must be used when tying bi-directional signals to power or ground. when tying any signal to power or ground, a resistor will also allow for system testab ility. for unused pins, it is suggested that ~ 10 k w resistors be used for pull-ups (except for picd[1:0] as discussed above) and ~ 1 k w resistors be used for pull-downs. 2.8. pentium ? ii processor system bus signal groups in order to simplify the following discussion, the pentium ii processor system bus signals have been combined into groups by buffer type. all pentium ii processor system bus outputs are open drain and require a high-level source provided externally by the termination or pull-up resistor. gtl+ input signals have differential input buffers, which use v ref as a reference signal. gtl+ output signals require termination to 1.5 v. in this document, the term gtl+ input refers to the gtl+ input group as well as the gtl+ i/o group when receiving. similarly, gtl+ output refers to the gtl+ output group as well as the gtl+ i/o group when driving. emi pins should be connected to motherboard ground and/or to chassis ground through zero ohm (0 w) resistors. the zero ohm resistors should be placed in close proximity to the slot 1 connector. the path to chassis ground should be short in length and have a low impedance. the cmos, clock, apic and jtag inputs can each be driven from ground to 2.5 v. the cmos, apic and jtag outputs are open drain and should be pulled high to 2.5 v. this ensures not only correct operation for the pentium ii processor, but compatibility for future slot 1 products as well. see table 3 for recommended pull-up resistor values on each cmos signal. 150 w resistors are expected on the picd[1:0] lines. other values in table 3 are specified for proper logic analyzer and test mode operation only. the groups and the signals contained within each group are shown in table 4. refer to appendix a for descriptions of these signals.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 19 intel secret (until publication date) table 4. pentium ? ii processor/slot 1 system bus signal groups group name signals gtl+ input bpri#, br1# , defer#, reset#, rs[2:0]#, rsp#, trdy# gtl+ output prdy# gtl+ i/o a[35:3]#, ads#, aerr#, ap[1:0]#, berr#, binit#, bnr#, bp[3:2]#, bpm[1:0]#, br0# 1 , d[63:0]#, dbsy#, dep[7:0]#, drdy#, frcerr, hit#, hitm#, lock#, req[4:0]#, rp# cmos input a20m#, flush#, ignne#, init#, lint0/intr, lint1/nmi, preq#, pwrgood 2 , smi#, slp# 3 , stpclk# cmos output ferr#, ierr#, thermtrip# 4 host bus clock bclk apic clock picclk apic i/o 5 picd[1:0] tap input 5 tck, tdi, tms, trst# tap output 5 tdo power/other 6 vcc core , vcc l2 , vcc 5 , vid[4:0], v tt , v ss , slotocc#, testhi, bsel#, emi notes: 1. the br0# pin is the only breq signal that is bi-directional. the internal breq# signals are mapped onto br# pins after the agent id is determined. see appendix a for more information. 2. see section a.1.35 for information on the pwrgood signal. 3. see section 2.2.5 and section a.1.42 for information on the slp# signal. 4. see section a.1.49 for information on the thermtrip# signal. 5. these signals are specified for 2.5 v operation. see table 3 for recommended pull-up resistor values. 6. vcc core is the power supply for the processor core and l2 cache i/o logic. vcc l2 is the power supply for the l2 cache component core logic. vid[4:0] is described in section 2.6. v tt is used to terminate the system bus and generate v ref on the processor substrate. v ss is system ground. testhi should be connected to 2.5 v with a 1kC10k ohm resistor. vcc5 is not connected to the pentium ? ii processor. this supply is used for the debug purposes only. slotocc# is described in section a.1.41. bsel# should be connected at v ss . see appendix a for emi pin descriptions.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 20 intel secret (until publication date) 2.8.1. asynchronous vs. synchronous for system bus signals all gtl+ signals are synchronous to bclk. all of the cmos, clock, apic and tap signals can be applied asynchronously to bclk, except when running two processors in frc mode. synchronization logic is required on all signals going to both processors in order to run in frc mode. also note the timing requirements for frc mode operation. with frc enabled, picclk must be ? of bclk and synchronized with respect to bclk. picclk must always lag bclk as specified in table 15. all apic signals are synchronous to picclk. all tap signals are synchronous to tck. 2.9. test access port (tap) connection due to the voltage levels supported by other components in the test access port (t ap) logic, it is recommended that the pentium ii processor be first in the tap chain and followed by any other components within the system. a translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting a 2.5 v input. similar considerations must be made for tck, tms and trst#. two copies of each signal may be required with each driving a different voltage level. a debug port is described in the pentium ? ii processor developers manual (order number 243341). the debug port will have to be placed at the start and end of the tap chain with the tdi of the first component coming from the debug port and the tdo from the last component going to the debug port. in a 2-way mp system, be cautious when including an empty slot 1 connector in the scan chain. all connectors in the scan chain must have a processor installed to complete the chain or the system must s upport a method to bypass empty connectors; the slot 1 terminator substrate connects tdi to tdo. see the pentium ? ii processor developers manual (order number 243341) for more details. 2.10. maximum ratings table 5 contains pentium ii processor stress ratings only. functional operation at the absolute maximum and minimum is not implied nor guaranteed. the processor should not receive a clock while subjected to these conditions. functional operating conditions are given in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. 2.11. processor dc specifications the processor dc specifications in this section are defined at the pentium ii processor edge fingers. see appendix a for the processor edge finger signal definitions. most of the signals on the pentium ii processor system bus are in the gtl+ signal group. these signals are specified to be terminated to 1.5 v. the dc specifications for these signals are listed in table 8. to allow connection with other devices, the clock, cmos, apic and tap are designed to interface at non-gtl+ levels. the dc specifications for these pins are listed in table 8. table 6 through table 9 list the dc specifications for the pentium ii processor. specifications are valid only while meeting specifications for case temperature, clock frequency and input voltages. care should be taken to read all notes associated with each parameter.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 21 intel secret (until publication date) table 5. pentium ? ii processor absolute maximum ratings symbol parameter min max unit notes t storage processor storage temperature C40 85 c v cc(all) any processor supply voltage with respect to v ss C0.5 operating voltage +1.4 operating voltage +1.0 v v 1, 2, 7 1,2,8 v in gtl+ gtl+ buffer dc input voltage with respect to v ss C0.5 -0.3 3.3 vcc core +0.7 v v 7 8 v in cmos cmos buffer dc input voltage with respect to v ss C0.5 -0.3 3.3 3.3 v v 3, 7 3, 8 i vid max vid pin current 5 ma i slotocc max slotocc# pin current 5 ma mech max latch arms mechanical integrity of latch arms 50 cycles 4 mech max edge fingers mechanical integrity of substrate edge fingers 50 insertion/ extraction 5, 6 notes: 1. operating voltage is the voltage to which the component is designed to operate. see table 6. 2. this rating applies to the vcc core , vcc l2 , vcc 5 and any input (except as noted below) to the processor. 3. parameter applies to cmos, apic and tap bus signal groups only. 4. the mechanical integrity of the latch arms is specified to last a maximum of 50 cycles. 5. the electrical and mechanical integrity of the substrate edge fingers is specified to last for 50 insertion/extraction cycles . 6. intel has performed internal testing showing functionality of single s.e.c. cartridge processors after 5000 insertions. while insertion/extraction cycling above 50 insertions may cause an increase in the contact resistance (above 0.1 ohms) and a degradation in the material integrity of the edge finger gold plating, it is possible to have processor functionality above the specified limit. the actual number of insertions before processor failure will vary based upon system configuration and environmental conditions. 7. this specification applies to cpu id 63x. 8. this specification applies to cpu id 65x.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 22 intel secret (until publication date) table 6. pentium ? ii processor voltage and current specifications 1 symbol parameter core freq min typ max unit notes vcc core v cc for processor core 233 mhz 266 mhz 266 mhz 300 mhz 300 mhz 333 mhz 2.80 2.80 2.00 2.80 2.00 2.00 v v v v v v 2, 3, 15, 17 2, 3, 15, 17 2, 3, 15, 18 2, 3, 15, 17 2, 3, 15, 18 2, 3, 15, 18 vcc l2 v cc for l2 cache 3.135 3.30 3.465 v 3 v tt bus termination voltage 1.365 1.5 1.635 v 1.5 v 3%, 9% 4 baseboard tolerance, static baseboard voltage, static tolerance level C0.070 0.100 v 5 baseboard tolerance, transient baseboard voltage, transient tolerance level 233 mhz 266 mhz 266 mhz 300 mhz 333 mhz C0.150 -0.150 -0.120 -0.145 -0.120 0.150 0.150 0.120 0.145 0.120 v v v v v 5, 17 5, 17 5, 18 5, 17 5, 18 vcc core tolerance, static vcc core voltage, static tolerance level 233 mhz 266 mhz 266 mhz 300 mhz 333 mhz C0.090 -0.090 -0.085 -0.090 -0.085 0.100 0.100 0.100 0.100 0.100 v v v v v 6, 17 6, 17 6, 18 6, 18 6, 18 vcc core tolerance, transient vcc core voltage, transient tolerance level 233 mhz 266 mhz 266 mhz 300 mhz 333 mhz C0.195 -0.195 -0.140 -0.185 -0.140 0.195 0.195 0.140 0.185 0.140 v v v v v 6, 17 6, 17 6, 18 6, 17 6, 18 icc core i cc for vcc core 233 mhz 266 mhz 266 mhz 300 mhz 333 mhz 11.8 12.7 8.492 14.2 9.303 a a a a a 2, 7, 8, 16, 17 2, 7, 8, 16, 17 2, 7, 8, 16, 18 2, 7, 8, 16, 17 2, 7, 8, 16, 18 icc l2 i cc for l2 cache 1.4 1.0 a a 3, 8, 17 3, 8, 18 iv tt termination voltage supply current 2.7 2.677 a a 9, 17 9, 18
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 23 intel secret (until publication date) table 6. pentium ? ii processor voltage and current specifications 1 (contd) symbol parameter core freq min typ max unit notes icc dslp core i cc for deep sleep vcc core 0.35 0.35 a a 8, 17 8, 18 icc sgnt l2 i cc for stop-grant for vcc l2 0.2 tbd a a 10, 17 10, 18 icc slp l2 i cc for sleep vcc l2 0.2 tbd a a 8, 17 8, 18 icc dslp l2 i cc for deep sleep vcc l2 0.1 tbd a a 8, 17 8, 18 dlcc core /dt power supply current slew rate 30 20 a/s a/s 11, 12, 13, 17 11, 12, 13, 18 dlcc l2 /dt l2 cache power supply current slew rate 1 a/s 11, 12, 13 dlcc vtt /dt termination current slew rate 8 a/s see table 9 12, 13 vcc 5 5 v supply voltage 4.75 5.00 5.25 v 14 icc 5 i cc for 5 v supply voltage 1.0 a 14
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 24 intel secret (until publication date) notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. icc core and vcc core supply the processor core and the l2 cache i/o buffers. 3. vcc l2 and icc l2 supply the l2 cache core. 4. v tt must be held to 1.5 v 9%. it is recommended that v tt be held to 1.5 v3% during system bus idle. 5. these are the tolerance requirements, across a 20 mhz bandwidth, at the slot 1 connector pins on the bottom side of the baseboard . the requirements at the slot 1 connector pins account for voltage drops (and impedance discontinuities) across the connector, substrate edge fingers and to the processor core. the slot 1 connector has the following requirements: pin self inductance: 10.5 nh(max); pin to pin capacitance: 2pf (max, at 1 mhz); contact resistance: 12 m w (max averaged over power/ground contacts). contact intel for testing conditions of these requirements. 6. these are the tolerance requirements, across a 20 mhz bandwidth, at the processor substrate edge fingers . the requirements at the processor substrate edge fingers account for voltage drops (and impedance discontinuities) at the substrate edge fingers and to the processor core. 7. the typical icc core measurements are an average current draw during the execution of winstone* 96 on a windows* 95 operating system. these numbers are meant as a guideline only, not a guaranteed specification. actual measurements will vary based upon system environmental conditions and configuration. 8. max i cc measurements are measured at v cc nominal voltage under maximum signal loading conditions. 9. the current specified is the current required for a single pentium ? ii processor. a similar current is needed for the opposite end of the gtl+ bus. 10. the current specified is also for autohalt power down state. 11. maximum values are specified by design/characterization at nominal vcc core and nominal vcc l2 . 12. based on simulation and averaged over the duration of any change in current. use to compute the maximum inductance tolerable and reaction time of the voltage regulator. this parameter is not tested. 13. di cc /dt is measured at the slot 1 connector pins. 14. vcc 5 and icc 5 are not used by the pentium ii processor. this supply is used for debug purposes only. 15. use typical voltage specification with tolerance level specification to provide correct voltage regulation to the processor. 16. voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output voltage, at maximum current output, is no greater than the nominal voltage level of vcc core (vcc core_typ ). in this case, the maximum current level for the regulator, icc core_reg , can be reduced from the specified maximum current icc core_max and is calculated by the equation: icc core_reg = icc core_max x vcc core_typ / vcc core_max 17. this specification applies to cpu id 63x. 18. this specification applies to cpu id 65x.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 25 intel secret (until publication date) table 7. gtl+ signal groups dc specifications symbol parameter min max unit notes v il input low voltage C0.3 0.82 v v ih input high voltage 1.22 v tt v v ol output low voltage 0.60 v 1 v oh output high voltage v tt v tt + 0.015 v tt v tt v v 4, 5 4,6 i ol output low current 36 48 55 ma 12 i l leakage current 100 a 2 i lo output leakage current 15 a 3 notes: 1. parameter measured into a 50 w resistor to 1.5 v. 2. (0 v in 2.5 v +5%). 3. (0 v out 2.5 v +5%). 4. see v tt max in table 9. 5. this specification applies to cpu id 63x. 6. this specification applies to cpu id 65x. table 8. non-gtl+ signal groups dc specifications symbol parameter min max unit notes v il input low voltage C0.3 0.7 v v ih input high voltage 1.7 2.625 v 2.5 v +5% maximum v ol output low voltage 0.4 v 1 v oh output high voltage n/a 2.625 v all outputs are open- drain to 2.5 v +5% i ol output low current 14 ma i li input leakage current 100 a 2 i lo output leakage current 15 a 3 notes: 1. parameter measured at 14 ma (for use with ttl inputs). 2. (0 v in 2.5 v +5%). 3. (0 v out 2.5 v +5%).
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 26 intel secret (until publication date) 2.12. gtl+ system bus specifications it is recommended to have the gtl+ bus routed in a daisy-chain fashion with termination resistors at each end of every signal trace. these termination resistors are placed electrically between the ends of the signal traces and the v tt voltage supply and generally are chosen to approximate the substrate impedance. the valid high and low levels are determined by the input buffers using a reference voltage called v ref . table 9 lists the nominal specification for the gtl+ termination voltage (v tt ). the gtl+ reference voltage (v ref ) should be set to 2/3 v tt for the core logic using a voltage divider on the motherboard. it is important that the motherboard impedance be specified and held to a 20% tolerance, and that the intrinsic trace capacitance for the gtl+ signal group traces is known. for more details on gtl+, see the pentium ? ii processor developers manual (order number 243341) and the pentium ? ii processor gtl+ guidelines (order number 243330). 2.13. pentium ? ii processor system bus ac specifications the system bus timings specified in this section are defined at the processor edge fingers. timings will be tested at the processor core during manufacturing. timings at the processor edge fingers will be specified by design characterization. see appendix a for the pentium ii processor edge finger signal definitions. table 10 through table 15 list the ac specifications associated with the pentium ii processor system bus. the system bus ac specifications are broken into the following categories: table 10 and table 11 contain the system bus clock core frequency and cache bus frequencies; table 12 contains the gtl+ specifications table 13 contains the cmos signal group specifications; table 14 contains timings for the reset conditions; table 15 covers apic bus timing; table 16 covers tap timing. all system bus ac specifications for the gtl+ signal group are relative to the rising edge of the bclk input. all gtl+ timings are referenced to v ref for both 0 and 1 logic levels unless otherwise specified. the timings specified in this section should be used in conjunction with the i/o buffer models provided by intel. these i/o buffer models, which include package information, are available in ibis format on intels web site: http://www.intel.com. gtl+ layout guidelines are also available in ap-585, pentium ? ii processor gtl+ guidelines (order number 243330). care should be taken to read all notes associated with a particular timing parameter. table 9. pentium ? ii processor gtl+ bus specifications 1 symbol parameter min typ max units notes v tt bus termination voltage 1.365 1.5 1.635 v 1.5 v 3%, 9% 2 r tt termination resistor 56 ohms 5% v ref bus reference voltage 2/3 v tt v 2% 3 notes: 1. the pentium ? ii processor contains gtl+ termination resistors at the end of the signal trace on the processor substrate. the pentium ii processor generates v ref , on the processor, by using a voltage divider on v tt supplied through the slot 1 connector. 2. v tt must be held to 1.5 v 9%; dicc vtt /dt is specified in table 6. it is recommended that v tt be held to 1.5 3% during system bus idle. 3. v ref is generated by the processor to be 2/3 v tt nominally.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 27 intel secret (until publication date) table 10. system bus ac specifications (clock) 1, 2 t# parameter min nom max unit figure notes system bus frequency 66.67 mhz all processor core frequencies 3 t1: bclk period 15.0 ns 7 3, 4 t1b: bclk to core logic offset 0.78 ns 6 absolute value 5, 6 t2: bclk period stability 300 ps 7, 8 t3: bclk high time 4.70 ns 7 @>1.8 v t4: bclk low time 5.10 ns 7 @<0.7 v t5: bclk rise time 0.75 1.95 ns 7 (0.7 vC1.8 v) 9 t6: bclk fall time 0.75 1.95 ns 7 (1.8 vC0.7 v) 9 notes: 1. all ac timings for the gtl+ signals are referenced to the bclk rising edge at 0.70 v at the processor edge fingers. this reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 v. all gtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00 v at the processor edge fingers. 2. all ac timings for the cmos signals are referenced to the bclk rising edge at 0.70 v at the processor edge fingers. this reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to reference voltage of 1.25 v. all cmos signal timings (address bus, data bus, etc.) are referenced at 1.25 v at the processor edge fingers. 3. the internal core clock frequency is derived from the system bus clock. the system bus clock to core clock ratio is determined during initialization as described in section 2.5. table 11 shows the supported ratios for each processor. 4. the bclk period allows a +0.5 ns tolerance for clock driver variation. 5. the bclk offset time is the absolute difference needed between the bclk signal rising edge arriving at the slot 1 edge finger at 0.7 v vs. arriving at the core logic at 1.25 v. the positive offset is needed to account for the delay between the slot 1 connector and processor core. the positive offset ensures both the processor core and the core logic receive the bclk edge concurrently. 6. see section 3.1. for system bus clock signal quality specifications. 7. due to the difficulty of accurately measuring processor clock jitter in a system, it is recommended that a clock driver be used that is designed to meet the period stability specification into a test load of 10 to 20 pf. this should be measured on the rising edges of adjacent bclks crossing 1.25 v. the jitter present must be accounted for as a component of bclk timing skew between devices. 8. the clock drivers closed loop jitter bandwidth must be set low to allow any pll-based device to track the jitter created by the clock driver. the -20 db attenuation point of the clock driver, as measured into a 10 to 20 pf load, should be less than 500 khz. this specification may be ensured by design and/or measured with a spectrum analyzer. 9. not 100% tested. specified by design/characterization as a clock driver requirement.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 28 intel secret (until publication date) table 11. valid slot 1 system bus, core frequency and cache bus frequencies 1, 2 bclk frequency (mhz) frequency multipliers supported core frequency rating (mhz) l2 cache frequency (mhz) 66.67 7/2 233.33 116.67 3 66.67 4 266.66 133.33 3 66.67 4 266.67 133.33 4 66.67 9/2 300.00 150.00 3 66.67 5 333.33 166.67 4 notes: 1. contact your local intel representative for the latest information on processor frequencies and/or frequency multipliers. 2. while other bus ratios are defined, operation at frequencies other than those listed are not supported. 3. this specification applies to cpu id 63x. 4. this specification applies to cpu id 65x. table 12. gtl+ signal groups system bus ac specifications 1, 2 t# parameter min max unit figure notes t7: gtl+ output valid delay 1.07 6.37 ns 8 3 t8: gtl+ input setup time 2.53 ns 9 4, 5, 6 t9: gtl+ input hold time 1.53 ns 9 7 t10: reset# pulse width 1.00 ms 12 8 notes: 1. not 100% tested. specified by design characterization. 2. all ac timings for the gtl+ signals are referenced to the bclk rising edge at 0.70 v at the processor edge fingers. all gtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00 v at the processor edge fingers. 3. valid delay timings for these signals are specified into 50 w to 1.5 v. 4. a minimum of 3 clocks must be specified between two active-to-inactive transitions of trdy#. 5. reset# can be asserted (active) asynchronously, but must be deasserted synchronously. 6. specification is for a minimum 0.40 v swing. 7. specification is for a maximum 1.0 v swing. 8. after vcc core , vcc l2 and bclk become stable.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 29 intel secret (until publication date) table 13. system bus ac specifications (cmos signal group) 1, 2, 3 t# parameter min max unit figure notes t11: 2.5 v output valid delay 1.00 10.5 ns 8 4 t12: 2.5 v input setup time 5.50 ns 9 5, 6 t13: 2.5 v input hold time 1.75 ns 9 5 t14: 2.5 v input pulse width, except pwrgood 2 bclks 8 active and inactive states t15: pwrgood inactive pulse width 10 bclks 8 13 7 notes: 1. not 100% tested. specified by design characterization. 2. all ac timings for the cmos signals are referenced to the bclk rising edge at 0.7 v at the processor edge fingers. all cmos signal timings (address bus, data bus, etc.) are referenced at 1.25 v at the processor edge fingers. 3. these signals may be driven asynchronously, but must be driven synchronously in frc mode. 4. valid delay timings for these signals are specified to 2.5 v +5%.. see table 3 for pull-up resistor values. 5. to ensure recognition on a specific clock, the setup and hold times with respect to bclk must be met. 6. intr and nmi are only valid during apic disable mode. lint[1:0]# are only valid during apic enabled mode. 7. when driven inactive or after vcc core , vcc l2 and bclk become stable. table 14. system bus ac specifications (reset conditions) t# parameter min max unit figure notes t16: reset configuration signals (a[14:5]#, br0#, flush#, init#) setup time 4 bclks 11 before deassertion of reset# t17: reset configuration signals (a[14:5]#, br0#, flush#, init#) hold time 2 20 bclks 11 after clock that deasserts reset# t18: reset configuration signals (a20m#, ignne#, lint[1:0]#) setup time 1 ms 12 before deassertion of reset# t19: reset configuration signals (a20m#, ignne#, lint[1:0]#) delay time 5 bclks 12 after assertion of reset# 1 t20: reset configuration signals (a20m#, ignne#, lint[1:0]#) hold time 2 20 bclks 12 11 after clock that deasserts reset# note: 1. for a reset, the clock ratio defined by these signals must be a safe value (their final or lower multiplier) within this dela y unless pwrgood is being driven inactive.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 30 intel secret (until publication date) table 15. system bus ac specifications (apic clock and apic i/o) 1, 2 t# parameter min max unit figure notes t21: picclk frequency 2.0 33.3 mhz 3 t21b: frc mode bclk to picclk offset 1.0 5.0 ns 10 3 t22: picclk period 30.0 500.0 ns 7 t23: picclk high time 12.0 ns 7 t24: picclk low time 12.0 ns 7 t25: picclk rise time 1.0 5.0 ns 7 t26: picclk fall time 1.0 5.0 ns 7 t27: picd[1:0] setup time 8.5 ns 9 4 t28: picd[1:0] hold time 3.0 ns 9 4 t29: picd[1:0] valid delay 3.0 12.0 ns 8 4, 5, 6 notes: 1. not 100% tested. specified by design characterization. 2. all ac timings for the cmos signals are referenced to the picclk rising edge at 0.70 v at the processor edge fingers. all cmos signal timings (address bus, data bus, etc.) are referenced at 1.25 v at the processor edge fingers. 3. with frc enabled picclk must be 1/4x bclk and synchronized with respect to bclk. 4. referenced to picclk rising edge. 5. for open drain signals, valid delay is synonymous with float delay. 6. valid delay timings for these signals are specified to 2.5 v +5%. see table 3 for recommended pull-up resistor values.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 31 intel secret (until publication date) table 16. system bus ac specifications (tap connection) 1 t# parameter min max unit figure notes t30: tck frequency 16.667 mhz t31: tck period 60.0 ns 7 t32: tck high time 25.0 ns 7 @1.7 v 2 t33: tck low time 25.0 ns 7 @0.7 v 2 t34: tck rise time 5.0 ns 7 (0.7 vC1.7 v) 2 t35: tck fall time 5.0 ns 7 (1.7 vC0.7 v) 2 t36: trst# pulse width 40.0 ns 14 asynchronous 2 t37: tdi, tms setup time 5.5 ns 13 4 t38: tdi, tms hold time 14.5 ns 13 4 t39: tdo valid delay 2.0 13.5 ns 13 5, 6 t40: tdo float delay 28.5 ns 13 2, 5, 6 t41: non-test outputs valid delay 2.0 27.5 ns 13 5, 7, 8 t42: non-test inputs setup time 27.5 ns 13 2, 5, 7, 8 t43: non-test inputs setup time 5.5 ns 13 4, 7, 8 t44: non-test inputs hold time 14.5 ns 13 4, 7, 8 notes: 1. all ac timings for the tap signals are referenced to the tck rising edge at 0.70 v at the processor edge fingers. all tap signal timings (address bus, data bus, etc.) are referenced at 1.25 v at the processor edge fingers. 2. not 100% tested. specified by design characterization. 3. referenced to tck rising edge. 4. referenced to tck falling edge. 5. valid delay timing for this signal is specified to 2.5 v +5%. see table 3 for pull-up resistor values. 6. non-test outputs and inputs are the normal output or input signals (besides tck, trst#, tdi, tdo and tms). these timings correspond to the response of these signals due to tap operations. 7. during debug port operation, use the normal specified timings rather than the tap signal timings.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 32 intel secret (until publication date) bclk at slot 1 0.7v bclk at core logic 1.25v t1b 000807 figure 6. bclk to core logic offset notes for figure 7 through figure 14 1. figure 7 through figure 12 are to be used in conjunction with table 8 through table 16. 2. all ac timings for the gtl+ signals are referenced to the bclk rising edge at 0.70 v at the processor edge fingers. this reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to receive the signal with a reference at 1.25 v. timings for other components on the baseboard should use a bclk reference voltage of 1.25 v. all gtl+ signal timings (address bus, data bus, etc.) are referenced at 1.00 v at the slot 1 connector pin. 3. these measurements are collected at the pentium ? ii processor edge fingers. clk 1.8v 0.7v 1.25v t h t l t p t r t f t r t5, t25, t34 (rise time) t f t6, t26, t35 (fall time) t3, t23, t32 (high time) t h t4, t24, t33 (low time) t l t1, t22, t31 (blck, tck, picclk period) = = = = = t p 000761b figure 7. bclk, tck, picclk generic clock wave form
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 33 intel secret (until publication date) clk signal t x t x v valid valid t x t7, t11, t29 (valid delay) = t pw t14, t15 (pulse wdith) = v 1.0v for gtl+ signal group; 1.25v for cmos, apic and tap signal groups = t pw 000762b figure 8. system bus valid delay timings clk signal v valid t s t8, t12, t27 (setup time) = t h t9, t13, t28 (hold time) = v 1.0v for gtl+ signal group; 1.25v for cmos, apic and tap signal groups = t h t s 000763b figure 9. system bus setup and hold timings
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 34 intel secret (until publication date) bclk picclk 0.7 v 0.7 v lag lag = t21b (frc mode bclk to picclk offset) 000919 figure 10. frc mode bclk to picclk timing bclk reset# configuration (a20m#, ignne#, lint[1:0]#) configuration (a[14:5], br0#, flush#, [1:0]#) t t t9 (gtl+ input hold time) = t u t8 (gtl+ input setup time) = t v t10 (reset# pulse width) = t w t16 (reset configuration signals (a[14:5]#, br0#, flush#, init#) setup time) = t x t17 (reset configuration signals (a[14:5]#, br0#, flush#, init#) hold time) = t20 (reset configuration signals (a20m#, ignne#, lint[1:0]#) hold time) t y = t19 (reset configuration signals (a20m#, ignne#, lint[1:0]#) delay time) t z = t18 (reset configuration signals (a20m#, ignne#, lint[1:0]#) setup time) t y t z t v t x t t t u t w valid valid safe pcb-764 figure 11. system bus reset and configuration timings
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 35 intel secret (until publication date) bclk pwrgood reset# configuration (a20m#, ignne#, lint[1:0]#) t a t b t c t a t15 (pwrgood inactive pulse width) = t b t10 (reset# pulse width) = t c t20 (reset configuration signals (a20m#, ignne#, lint[1:0#]) hold time) = valid ratio v , ref v , core cc v cc l2 000765b figure 12. power-on reset and configuration timings
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 36 intel secret (until publication date) tck tdi, tms input signals tdo output signals 1.25 v t v t w t r t s t x t u t y t z 1.8 v t r t43 (all non-test inputs setup time) = t s t44 (all non-test inputs hold time) = t u t40 (tdo float delay) = t v t37 (tdi, tms setup time) = t w t38 (tdi, tms hold time) = t x t39 (tdo valid delay) = t y t41 (all non-test outputs valid delay) = t z t42 (all non-test outputs float delay) = 000766b figure 13. test timings (tap connection) trst# 1.25v t q t q t37 (trst# pulse width) = pcb-773 figure 14. test reset timings
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 37 intel secret (until publication date) 3.0. system bus signal simulations many scenarios have been simulated to generate a set of gtl+ layout guidelines which are available in the pentium ? ii processor gtl+ guidelines (order number 243330). refer to the pentium ? ii processor developers manual (order number 243341) for the gtl+ buffer specification. all wave terms described below are simulated at the contact to the processor edge fingers. 3.1. system bus clock (bclk) signal quality specifications table 17 describes the signal quality for the system bus clock (bclk) signal. figure 15 describes the signal quality wave form for the system bus clock. table 17. bclk signal quality specifications t# parameter min nom max unit figure notes v1: bclk v il 0.7 v 7 v2: bclk v ih 1.8 v 7 v3: v in absolute voltage range C0.5 3.3 v 7 overshoot, undershoot v4: rising edge ringback 2.0 v 7 absolute value 1 v5: falling edge ringback 0.5 v 7 absolute value 1 v6: tline ledge voltage 1.0 1.7 v 7 at ledge midpoint 2 v7: tline ledge oscillation 0.2 v 7 peak-to-peak 3 notes: 1. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal can dip back to after passing the v ih (rising) or v il (falling) voltage limits. 2. the bclk at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. the midpoint voltage level of this ledge must be within the range specified. 3. the ledge (v13) is allowed to have peak-to-peak oscillation as specified. t3 v3 v5 v3 v 2 v 1 v7 v6 t6 t4 t5 v4 000808 figure 15. bclk, tck, picclk generic clock wave form at the processor edge fingers
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 38 intel secret (until publication date) table 18. gtl+ signal groups ringback tolerance t# parameter min unit figure notes a : overshoot 100 mv 16 1, 2 t : minimum time at high 1.5 ns 16 1, 2 r : amplitude of ringback C250 mv 16 1, 2, 3 f : final settling voltage 250 mv 16 1, 2 d : duration of sequential ringback n/a ns 16 1, 2 notes: 1. specified for the edge rate of 0.3 C 0.8 v/ns. see figure 16 for the generic wave form. 2. all values determined by design/characterization. 3. ringback v ref +250 mv is not authorized. clk ref t a r f v start v +0.2 ref v ref v C0.2 ref time clock d 0.7v clk ref note: high to low case is analogous. 000914a figure 16. low to high gtl+ receiver ringback tolerance
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 39 intel secret (until publication date) 3.2. gtl+ signal quality specifications table 18 and figure 16 describe the gtl+ signal quality specifications for the pentium ii processor. for more information on the gtl+ interface, see the pentium ? ii processor developers manual (order number 243341). 3.3. non-gtl+ signal quality specifications signals driven on the pentium ii processor system bus should meet signal quality specifications to ensure that the components read data properly and that incoming signals do not affect the long term reliability of the component. there are three signal quality parameters defined: overshoot/undershoot, ringback and settling limit. all three signal quality parameters are shown in figure 17 for non-gtl+ signal groups. 3.3.1. o vershoot/undershoot guidelines overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high voltage or below v ss . the overshoot/undershoot guideline limits transitions beyond v cc or v ss due to the fast signal edge rates. (see figure 17 for non-gtl+ signals.) the processor can be damaged by repeated overshoot events on 2.5 v tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). however, excessive ringback is the dominant detrimental system timing effect resulting from overshoot/undershoot (i.e., violating the overshoot/undershoot guideline will make satisfying the ringback specification difficult). the overshoot/ undershoot guideline is 0.8 v and assumes the absence of diodes on the input. these guidelines should be verified in simulations without the on- chip esd protection diodes present because the diodes will begin clamping the 2.5 v tolerant signals beginning at approximately 1.25 v above vcc core and 0.5 v below v ss . if signals are not reaching the clamping voltage, this will not be an issue. a system should not rely on the diodes for overshoot/ undershoot protection as this will negatively affect the life of the components and make meeting the ringback specification very difficult.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 40 intel secret (until publication date) undershoot overshoot settling limit settling limit rising-edge ringback falling-edge ringback v lo v ss time v = hi v cc 2.5 000767b figure 17. non-gtl+ overshoot/undershoot and ringback
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 41 intel secret (until publication date) 3.3.2. ringback specification ringback refers to the amount of reflection seen after a signal has switched. the ringback specification is the voltage that the signal rings back to after achieving its maximum absolute value. (see figure 18 for an illustration of ringback.) excessive ringback can cause false signal detection or extend the propagation delay. the ringback specification applies to the input pin of each receiving agent. violations of the signal ringback specification are not allowed under any circumstances for the non-gtl+ signals. ringback can be simulated with or without the input protection diodes that can be added to the input buffer model. however, signals that reach the clamping voltage should be evaluated further. see table 19 for the signal ringback specifications for non-gtl+ signals. 3.3.3. settling limit guideline settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach before its next transition. the amount allowed is 10 percent of the total signal swing (v hi Cv lo ) above and below its final value. a signal should be within the settling limits of its final value, when either in its high state or low state, before it transitions again. signals that are not within their settling limit before transitioning are at risk of unwanted oscillations which could jeopardize signal integrity. simulations to verify settling limit may be done either with or without the input protection diodes present. violation of the settling limit guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of the ringing increasing in the subsequent transitions. table 19. signal ringback specifications for non-gtl+ signals input signal group transition maximum ringback (with input diodes present) figure non-gtl+ signals 0 ? 1 2.0 v17 non-gtl+ signals 1 ? 0 0.7 v17
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 42 intel secret (until publication date) 4.0. thermal specifications and design considerations the pentium ii processor has a thermal plate for heatsink attachment. the thermal plate interface is intended to provide for multiple types of thermal solutions. this chapter will provide the necessary data for a thermal solution to be developed. see figure 18 for thermal plate location. 4.1. thermal specifications table 20 provides the thermal design power dissipation for the pentium ii processor. while the processor core dissipates the majority of the thermal power, the thermal power dissipated by the l2 cache also impacts the thermal plate power specification and the overall processor power specification. systems should design for the highest possible thermal power, even if a processor with a lower thermal dissipation is planned. the thermal plate is the attach location for all thermal solutions. the maximum allowed thermal plate temperature is specified in table 6. a thermal solution should be designed to ensure the temperature of the thermal plate never exceeds these specifications. the processor power is a result of heat dissipated through the thermal plate and other paths. the heat dissipation is a combination of heat from both the processor core and l2 cache. the overall system thermal design must comprehend the processor power. the combination of the processor core and the l2 cache dissipating heat through the thermal plate is the thermal plate power. the heatsink should be designed to dissipate the thermal plate power. see table 20 for pentium ii processor thermal design specifications. skirt left latch right latch cover thermal plate 000921 figure 18. processor s.e.c. cartridge thermal plate
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 43 intel secret (until publication date) table 20. pentium ? ii processor thermal design specification 1 processor core frequency (mhz) l2 cache size (kb) max processor power 2 (w) max thermal plate power 3 (w) min t plate (c) max t plate (c) min t cover (c) max t cover (c) 333 5 512 23.7 21.8 5 65 5 75 300 4 512 43.0 41.4 5 72 5 72 266 5 512 19.5 17.8 5 65 5 75 266 4 512 38.2 37.0 5 75 5 75 233 4 512 34.8 33.6 5 75 5 75 notes: 1. these values are specified at nominal vcc core for the processor core and nominal vcc l2 (3.3 v) for the l2 cache. 2. processor power is 100% of processor core and 100% l2 cache power. 3. thermal plate power is 100% of the processor core power and a percentage of the l2 cache power. 4. this specification applies to cpu id 63x. 5. this specification applies to cpu id 65x. 4.2. pentium ? ii processor thermal analysis 4.2.1. thermal solution performance all processor thermal solutions should attach to the thermal plate. the thermal solution must adequately control the thermal plate and cover temperatures below the maximum and above the minimum specified in table 20. the performance of any thermal solution is defined as the thermal resistance between the thermal plate and the ambient air around the processor ( q thermal plate to ambient ). the lower the thermal resistance between the thermal plate and the ambient air, the more efficient the thermal solution is. the required q thermal plate to ambient is dependent upon the maximum allowed thermal plate temperature (t plate ), the ambient temperature (t la ) and the thermal plate power (p plate ). q thermal plate to ambient = (tplate C tla) / pplate the maximum t plate and the thermal plate power are listed in table 20. t la is a function of the system design. table 21 provides the resultant thermal solution performance for a 266 mhz pentium ii processor at different ambient air temperatures around the processor. table 21. example thermal solution performance for 266 mhz pentium ? ii processor at thermal plate power of 37.0 watts thermal solution (performance) local ambient temperature (t la ) 35 c 40 c 45 c q thermal plate to ambient (c/watt) 1.08 0.95 0.81 the q thermal plate to ambient value is made up of two primary components: the thermal resistance between the thermal plate and heatsink ( q thermal plate to heatsink ) and the thermal resistance between the heatsink and the ambient air around the processor ( q heatsink to air ). a critical but controllable factor to decrease the resultant value of q thermal plate to heatsink is management of the thermal interface between the thermal plate and heatsink. thermal interfaces are addressed in ap-586, pentium ? ii processor thermal design guidelines (order number 243333). the other controllable factor ( q heatsink to air ) is resultant in the design of the heatsink and airflow around the heatsink. heatsink design constraints are also provided in ap-586, pentium ? ii processor thermal design guidelines (order number 243333).
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 44 intel secret (until publication date) 4.2.2. measurements for thermal specifications 4.2.2.1. thermal plate temperature measurement to ensure functional and reliable pentium ii processor operation, the thermal plate temperature (t plate ) must be maintained at or below the maximum t plate temperature specified in table 20. figure 19 shows the location for t plate measurement. special care is required when measuring t plate to ensure an accurate temperature measurement. thermocouples are used to measure t plate . before taking any temperature measurements, the thermocouples must be calibrated. when measuring the temperature of a surface, errors can be introduced in the measurement if not handled properly. the measurement errors can be due to a poor thermal contact between the thermocouple junction and the surface of the thermal plate, conduction through thermocouple leads, heat loss by radiation and convection, or by contact between the thermocouple cement and the heatsink base. to minimize these errors, the following approach is recommended: use 36 gauge or finer diameter k, t, or j type thermocouples. intels laboratory testing was done using a thermocouple made by omega* (part number: 5tc-ttk-36-36). attach the thermocouple bead or junction to the top surface of the thermal plate at the location specified in figure 19 using high thermal conductivity cements. the thermocouple should be attached at a 0 angle if no heatsink is attached to the thermal plate. if a heatsink is attached to the thermal plate but the heatsink does not cover the location specified for t plate measurement, the thermocouple should be attached at a 0 angle (refer to figure 20). 2.673 1.089 measure from edge of thermal plate. cover measure t at this point. plate processor core substrate all dimensions in inches. 0.35 r recommended location of thermal grease application. approx. location for recommended heatsink attachment. 000874b figure 19. processor thermal plate temperature measurement location
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 45 intel secret (until publication date) 000899 figure 20. technique for measuring t plate with 0 angle attachment 000900 figure 21. technique for measuring t plate with 90 angle attachment the thermocouple should be attached at a 90 angle if a heatsink is attached to the thermal plate and the heatsink covers the location specified for t plate measurement (refer to figure 21). the hole size through the heatsink base to route the thermocouple wires out should be smaller than 0.150" in diameter. make sure there is no contact between the thermocouple cement and heatsink base. this contact will affect the thermocouple reading. 4.2.2.2. cover temperature measurement the maximum and minimum s.e.c. cartridge cover temperature (t cover ) for the pentium ii processor is specified in table 20. this temperature specification is meant to ensure correct and reliable operation of the processor. figure 22 illustrates the hottest points on the s.e.c. cartridge cover. t cover thermal measurements should be made at these points. 4.3. thermal solution attach methods the design of the thermal plate is intended to support two different attach methods heatsink clips and rivscrews*. figure 41 shows the thermal plate and the locations of the attach features. only one attach method should be used for any thermal solution. 4.3.1. heatsink clip attach figure 23 and figure 24 illustrate example clip designs to support a low profile and a full height heatsink, respectively. the clips attach the heatsink by engaging with the underside of the thermal plate. the clearance of the thermal plate to the internal processor substrate is a minimum 0.124" (illustrated in figure 23 and figure 24). the clips should be designed such that they will engage within this space, and also not damage the substrate upon insertion or removal. finally, the clips should be able to retain the heatsink onto the thermal plate through a system level mec hanical shock and vibration test. the clips should also apply a high enough force to spread the interface material for the spot size selected.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 46 intel secret (until publication date) edge near slot 1 connector 0.8 2.8 1.0 1.31 0.8 1.0 000966 figure 22. guideline locations for cover temperature (t cover ) thermocouple placement 0.124 min gap thermal plate spring clip cover processor substrate all dimensions in inches. processor core 000877a figure 23. processor with an example low profile heatsink attached using spring clips
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 47 intel secret (until publication date) 0.124 min gap thermal plate spring clip cover processor substrate all dimensions in inches. processor core 000878a figure 24. processor with an example full height heatsink attached using spring clips 4.3.2. rivscrew* attach the rivscrew attach mec hanism uses a specialized rivet that is inserted through a hole in the heatsink into the thermal plate. upon insertion, a threaded fastener is formed that can be removed if necessary. for rivscrew attachment, the minimum gap between the thermal plate and the processor substrate is 0.139". for use of the advel ri vscrew (part number 1712-3510), the heatsink base thickness must be 0.140 0.010". see figure 25, figure 26 and figure 27 for details of heatsink requirements for use with rivscrews. for other heatsink base thickness, contact advel for other rivscrew parts that would be required.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 48 intel secret (until publication date) 3.0 maximum total heatsink depth 0.140 0.010 recommended heatsink base thickness all dimensions in inches. 0.305 gap in fins to allow for clearance of nose, rivscrew* and mandrel (minimum) 0.064 (including tolerance) 000901 figure 25. heatsink recommendations and guidelines for use with rivscrews* all dimensions in inches. heatsink base thermal plate processor core processor substrate 0.139 min. 0.140 0.010 heatsink base (recommended) 0.144 0.005 thermal grease mandrel rivscrew* 000915 figure 26. heatsink rivscrew* and thermal plate recommendations and guidelines
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 49 intel secret (until publication date) y x hole is 4 x 0.150 ? 0.005 0.305 heatsink all dimensions in inches. 000903 figure 27. general rivscrew* heatsink mechanical recommendations
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 50 intel secret (until publication date) figure 28. heatsink attachment mechanism design space
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 51 intel secret (until publication date) 5.0. s.e.c. cartridge mechanical specifications the pentium ii processor uses s.e.c. cartridge technology. the s.e.c. cartridge contains the processor core, l2 cache and other passive components. the s.e.c. cartridge connects to the motherboard through an edge connector. mechanical specifications for the processor are given in this section. see section 1.1.1. for a complete terminology listing. figure 29 shows the thermal plate side view and the cover side view of the processor. figure 30 shows the s.e.c. cartridge dimensions. figure 38 through figure 40 provide details of the s.e.c. cartridge substrate edge finger contacts. the processor edge connector defined in this document is referred to as slot 1. table 23 through table 26 provide the processor edge fingers and slot 1 connector signal definitions for the pentium ii processor. the signal locations on the slot 1 edge connector are to be used for signal routing, simulation and component placement on the motherboard. 5.1. s.e.c. cartridge materials information the s.e.c. cartridge is comprised of multiple pieces to make the complete assembly. this section will provide information relevant to the use and acceptance of the package. the complete s.e.c. cartridge assembly weighs approximately 150 grams. see table table 22 for further piece part information. table 22. s.e.c. cartridge materials s.e.c. cartridge piece piece material maximum piece weight (grams) thermal plate aluminum 6063-t6 67.0 latch arms ge lexan 940, 30% glass filled less than 2.0 per latch arm cover ge lexan 940 24.0 skirt ge lexan 940 6.5 table 23. s.e.c. cartridge dimensions symbol description min max figure a s.e.c. cartridge length 5.495 5.515 37 b s.e.c. cartridge height 2.457 2.489 31 c s.e.c. cartridge depth 0.637 0.657 30 d thermal plate length 5.324 5.354 37 e thermal plate height 1.917 1.927 31 note: 1. this table applies to the dimensions noted in figure 30 through figure 35.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 52 intel secret (until publication date) notes for figure 29 through figure 40 unless otherwise specified, the following drawings are dimensioned in inches. all dimensions provided with tolerances are guaranteed to be met for all normal production product. figures and drawings labeled as reference dimensions are provided for informational purposes. reference dimensions are extracted from the mechanical design database and are nominal dimensions with no tolerance information applied. reference dimensions are not checked as part of the processor manufacturing. drawings are not to scale. skirt left latch right latch cover thermal plate right latch left latch cover 000893a figure 29. s.e.c. cartridge C thermal plate and cover side views
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 53 intel secret (until publication date) top view cover side view thermal plate side view left right right side right left skirt thermal plate right latch left latch cover c 000894b figure 30. s.e.c. cartridge overall cartridge dimensions
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 54 intel secret (until publication date) 3.805 0.020 2x 0.340 0.005 2x 0.127 0.005 1.830 0.005 1.845 0.005 2x 0.265 0.005 1.235 0.020 2.473 0.016 2.070 0.020 these dimensions are from the bottom of the substrate edge fingers e b note: 1. see figure 34 for details. 000906 figure 31. s.e.c cartridge thermal plate side dimensions
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 55 intel secret (until publication date) detail a 6x 0.124 +0.001 C0.002 8x r 0.0625 0.002 4x 0.365 0.005 see detail a 2.110 0.008 0.000 0.978 0.008 0.500 0.008 0.250 0.008 0.000 0.375 0.008 note: 1. see figure 35 for details. 000907 figure 32. s.e.c. cartridge thermal plate and side view dimensions
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 56 intel secret (until publication date) 2.50 1.25 0.001 / 1.000 x 1.000 note: all dimensions without tolerance information are considered reference dimensions only. 000908 figure 33. s.e.c. cartridge thermal plate flatness dimensions
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 57 intel secret (until publication date) 0.236 0.113 0.060 0.022 detail a detail b (bottom side view) 0.084 0.060 0.122 0.075 r 0.015 0.060 0.055 0.316 0.058 0.277 0.116 0.291 detail c detail d detail e 45 0.120 min. 0.082 0.276 0.216 note: all dimensions without tolerance information are considered reference dimensions only. 000909 figure 34. s.e.c. cartridge latch details
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 58 intel secret (until publication date) 2x 0.174 0.005 2x 0.488 0.010 2x 0.238 0.010 2x 0.103 0.005 2x 0.64 7 0.015 2x 0.253 0.010 2x 0.058 0.005 2x 0.136 0.005 left 000910 figure 35. s.e.c. cartridge latch arm, thermal plate lug, and cover lug dimensions
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 59 intel secret (until publication date) icomp? 2.0 index=yyy sznnn/xyz order code xxxxxxxx-nnnn 2-d matrix mark hologram location pentium ? ii p r o c e s s o r i '94 '96 m c dynamic mark area pentium ? ii p r o c e s s o r with mmx? technology pentium ? ii p r o c e s s o r with mmx? technology 000911a figure 36. s.e.c. cartridge mark locations table 24. description table for processor markings code letter description a logo b product name c trademark d logo e product name f dynamic mark area C with 2-d matrix
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 60 intel secret (until publication date) skirt thermal plate 2.263 0.015 5.255 0.006 cover 3.243 0.015 5.344 0.010 5.505 0.010 bottom view left right a d 000870d figure 37. s.e.c. cartridge bottom side view
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 61 intel secret (until publication date) thermal plate 2.835 cover pin a121 pin a1 substrate 1.850 2.992 0.008 2.008 0.008 5.000 w x y z 70 0.062 +0.007 C0.005 see detail a in next figure note: all dimensions without tolerance information are considered reference dimensions only. 000814d figure 38. s.e.c. cartridge substrate dimensions pin b121 pin b1 substrate cover note: cover not completely shown to allow for substrate details to be shown. this drawing shows the pin details of the cover side of the s.e.c. cartridge. 000858c figure 39. s.e.c. cartridge substrate dimensions, cover side view
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 62 intel secret (until publication date) 0.146 max. 0.098 y pin a74 pin a73 0.098 w 0.039 0.037 121 x 0.016 0.002 0.045 0.236 0.074 0.002 .20 .008 lzwm .05 .002 pad to pad 121 x 0.043 0.002 .20 .008 lzwm .05 .002 pad to pad l l 0.356 min. 0.138 min. 0.008 (0.010) note: all dimensions without tolerance information are considered reference dimensions only. 000859b figure 40. substrate C s.e.c. cartridge substrate detail a
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 63 intel secret (until publication date) 5.2. processor edge finger signal listing table 25 is the processor substrate edge finger listing in order by pin number. table 25. signal listing in order by pin number pin no. pin name signal buffer type pin no. pin name signal buffer type a1 vcc_vtt gtl+ v tt supply b1 emi emi management a2 gnd v ss b2 flush# cmos input a3 vcc_vtt gtl+ v tt supply b3 smi# cmos input a4 ierr# cmos output b4 init# cmos input a5 a20m# cmos input b5 vcc_vtt gtl+ v tt supply a6 gnd v ss b6 stpclk# cmos input a7 ferr# cmos output b7 tck jtag input a8 ignne# cmos input b8 slp# cmos input a9 tdi jtag input b9 vcc_vtt gtl+ v tt supply a10 gnd v ss b10 tms jtag input a11 tdo jtag output b11 trst# jtag input a12 pwrgood cmos input b12 reserved reserved for future use a13 testhi cmos test input b13 vcc_core processor core v cc a14 gnd v ss b14 reserved reserved for future use a15 thermtrip# cmos output b15 reserved reserved for future use a16 reserved reserved for future use b16 lint[1]/nmi cmos input a17 lint[0]/intr cmos input b17 vcc_core processor core v cc a18 gnd v ss b18 picclk apic clock input a19 picd[0] cmos i/o b19 bp#[2] gtl+ i/o a20 preq# cmos input b20 reserved reserved for future use a21 bp#[3] gtl+ i/o b21 bsel# gnd a22 gnd v ss b22 picd[1] cmos i/o a23 bpm#[0] gtl+ i/o b23 prdy# gtl+ output a24 binit# gtl+ i/o b24 bpm#[1] gtl+ i/o a25 dep#[0] gtl+ i/o b25 vcc_core processor core v cc
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 64 intel secret (until publication date) table 25. signal listing in order by pin number (contd) pin no. pin name signal buffer type pin no. pin name signal buffer type a26 gnd v ss b26 dep#[2] gtl+ i/o a27 dep#[1] gtl+ i/o b27 dep#[4] gtl+ i/o a28 dep#[3] gtl+ i/o b28 dep#[7] gtl+ i/o a29 dep#[5] gtl+ i/o b29 vcc_core processor core v cc a30 gnd v ss b30 d#[62] gtl+ i/o a31 dep#[6] gtl+ i/o b31 d#[58] gtl+ i/o a32 d#[61] gtl+ i/o b32 d#[63] gtl+ i/o a33 d#[55] gtl+ i/o b33 vcc_core processor core v cc a34 gnd v ss b34 d#[56] gtl+ i/o a35 d#[60] gtl+ i/o b35 d#[50] gtl+ i/o a36 d#[53] gtl+ i/o b36 d#[54] gtl+ i/o a37 d#[57] gtl+ i/o b37 vcc_core processor core v cc a38 gnd v ss b38 d#[59] gtl+ i/o a39 d#[46] gtl+ i/o b39 d#[48] gtl+ i/o a40 d#[49] gtl+ i/o b40 d#[52] gtl+ i/o a41 d#[51] gtl+ i/o b41 emi emi management a42 gnd v ss b42 d#[41] gtl+ i/o a43 d#[42] gtl+ i/o b43 d#[47] gtl+ i/o a44 d#[45] gtl+ i/o b44 d#[44] gtl+ i/o a45 d#[39] gtl+ i/o b45 vcc_core processor core v cc a46 gnd v ss b46 d#[36] gtl+ i/o a47 reserved reserved for future use b47 d#[40] gtl+ i/o a48 d#[43] gtl+ i/o b48 d#[34] gtl+ i/o a49 d#[37] gtl+ i/o b49 vcc_core processor core v cc a50 gnd v ss b50 d#[38] gtl+ i/o a51 d#[33] gtl+ i/o b51 d#[32] gtl+ i/o a52 d#[35] gtl+ i/o b52 d#[28] gtl+ i/o
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 65 intel secret (until publication date) table 25. signal listing in order by pin number (contd) pin no. pin name signal buffer type pin no. pin name signal buffer type a53 d#[31] gtl+ i/o b53 vcc_core processor core v cc a54 gnd v ss b54 d#[29] gtl+ i/o a55 d#[30] gtl+ i/o b55 d#[26] gtl+ i/o a56 d#[27] gtl+ i/o b56 d#[25] gtl+ i/o a57 d#[24] gtl+ i/o b57 vcc_core processor core v cc a58 gnd v ss b58 d#[22] gtl+ i/o a59 d#[23] gtl+ i/o b59 d#[19] gtl+ i/o a60 d#[21] gtl+ i/o b60 d#[18] gtl+ i/o a61 d#[16] gtl+ i/o b61 emi emi management a62 gnd v ss b62 d#[20] gtl+ i/o a63 d#[13] gtl+ i/o b63 d#[17] gtl+ i/o a64 d#[11] gtl+ i/o b64 d#[15] gtl+ i/o a65 d#[10] gtl+ i/o b65 vcc_core processor core v cc a66 gnd v ss b66 d#[12] gtl+ i/o a67 d#[14] gtl+ i/o b67 d#[7] gtl+ i/o a68 d#[9] gtl+ i/o b68 d#[6] gtl+ i/o a69 d#[8] gtl+ i/o b69 vcc_core processor core v cc a70 gnd v ss b70 d#[4] gtl+ i/o a71 d#[5] gtl+ i/o b71 d#[2] gtl+ i/o a72 d#[3] gtl+ i/o b72 d#[0] gtl+ i/o a73 d#[1] gtl+ i/o b73 vcc_core processor core v cc a74 gnd v ss b74 reset# gtl+ input a75 bclk processor clock input b75 br1# gtl+ input a76 br0# gtl+ i/o b76 frcerr gtl+ i/o a77 berr# gtl+ i/o b77 vcc_core processor core v cc a78 gnd v ss b78 a#[35] gtl+ i/o a79 a#[33] gtl+ i/o b79 a#[32] gtl+ i/o
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 66 intel secret (until publication date) table 25. signal listing in order by pin number (contd) pin no. pin name signal buffer type pin no. pin name signal buffer type a80 a#[34] gtl+ i/o b80 a#[29] gtl+ i/o a81 a#[30] gtl+ i/o b81 emi emi management a82 gnd v ss b82 a#[26] gtl+ i/o a83 a#[31] gtl+ i/o b83 a#[24] gtl+ i/o a84 a#[27] gtl+ i/o b84 a#[28] gtl+ i/o a85 a#[22] gtl+ i/o b85 vcc_core processor core v cc a86 gnd v ss b86 a#[20] gtl+ i/o a87 a#[23] gtl+ i/o b87 a#[21] gtl+ i/o a88 reserved reserved for future use b88 a#[25] gtl+ i/o a89 a#[19] gtl+ i/o b89 vcc_core processor core v cc a90 gnd v ss b90 a#[15] gtl+ i/o a91 a#[18] gtl+ i/o b91 a#[17] gtl+ i/o a92 a#[16] gtl+ i/o b92 a#[11] gtl+ i/o a93 a#[13] gtl+ i/o b93 vcc_core processor core v cc a94 gnd v ss b94 a#[12] gtl+ i/o a95 a#[14] gtl+ i/o b95 a#[8] gtl+ i/o a96 a#[10] gtl+ i/o b96 a#[7] gtl+ i/o a97 a#[5] gtl+ i/o b97 vcc_core processor core v cc a98 gnd v ss b98 a#[3] gtl+ i/o a99 a#[9] gtl+ i/o b99 a#[6] gtl+ i/o a100 a#[4] gtl+ i/o b100 emi emi management a101 bnr# gtl+ i/o b101 slotocc# gnd a102 gnd v ss b102 req#[0] gtl+ i/o a103 bpri# gtl+ input b103 req#[1] gtl+ i/o a104 trdy# gtl+ input b104 req#[4] gtl+ i/o a105 defer# gtl+ input b105 vcc_core processor core v cc a106 gnd v ss b106 lock# gtl+ i/o
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 67 intel secret (until publication date) table 25. signal listing in order by pin number (contd) pin no. pin name signal buffer type pin no. pin name signal buffer type a107 req#[2] gtl+ i/o b107 drdy# gtl+ i/o a108 req#[3] gtl+ i/o b108 rs#[0] gtl+ input a109 hitm# gtl+ i/o b109 vcc5 other v cc a110 gnd v ss b110 hit# gtl+ i/o a111 dbsy# gtl+ i/o b111 rs#[2] gtl+ input a112 rs#[1] gtl+ input b112 reserved reserved for future use a113 reserved reserved for future use b113 vcc_l2 other v cc a114 gnd v ss b114 rp# gtl+ i/o a115 ads# gtl+ i/o b115 rsp# gtl+ input a116 reserved reserved for future use b116 ap#[1] gtl+ i/o a117 ap#[0] gtl+ i/o b117 vcc_l2 other v cc a118 gnd v ss b118 aerr# gtl+ i/o a119 vid[2] vcc core or v ss b119 vid[3] vcc core or v ss a120 vid[1] vcc core or v ss b120 vid[0] vcc core or v ss a121 vid[4] vcc core or v ss b121 vcc_l2 other v cc
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 68 intel secret (until publication date) table 26 is the processor substrate edge connector listing in order by pin name. table 26. signal listing in order by signal name pin no. pin name signal buffer type pin no. pin name signal buffer type b98 a#[3] gtl+ i/o b80 a#[29] gtl+ i/o a100 a#[4] gtl+ i/o a81 a#[30] gtl+ i/o a97 a#[5] gtl+ i/o a83 a#[31] gtl+ i/o b99 a#[6] gtl+ i/o b79 a#[32] gtl+ i/o b96 a#[7] gtl+ i/o a79 a#[33] gtl+ i/o b95 a#[8] gtl+ i/o a80 a#[34] gtl+ i/o a99 a#[9] gtl+ i/o b78 a#[35] gtl+ i/o a96 a#[10] gtl+ i/o a5 a20m# cmos input b92 a#[11] gtl+ i/o a115 ads# gtl+ i/o b94 a#[12] gtl+ i/o b118 aerr# gtl+ i/o a93 a#[13] gtl+ i/o a117 ap#[0] gtl+ i/o a95 a#[14] gtl+ i/o b116 ap#[1] gtl+ i/o b90 a#[15] gtl+ i/o a75 bclk processor clock input a92 a#[16] gtl+ i/o a77 berr# gtl+ i/o b91 a#[17] gtl+ i/o a24 binit# gtl+ i/o a91 a#[18] gtl+ i/o a101 bnr# gtl+ i/o a89 a#[19] gtl+ i/o b19 bp#[2] gtl+ i/o b86 a#[20] gtl+ i/o a21 bp#[3] gtl+ i/o b87 a#[21] gtl+ i/o a23 bpm#[0] gtl+ i/o a85 a#[22] gtl+ i/o b24 bpm#[1] gtl+ i/o a87 a#[23] gtl+ i/o a103 bpri# gtl+ input b83 a#[24] gtl+ i/o a76 br0# gtl+ i/o b88 a#[25] gtl+ i/o b75 br1# gtl+ input b82 a#[26] gtl+ i/o b21 bsel# gnd a84 a#[27] gtl+ i/o b72 d#[0] gtl+ i/o b84 a#[28] gtl+ i/o a73 d#[1] gtl+ i/o
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 69 intel secret (until publication date) table 26. signal listing in order by signal name (contd) pin no. pin name signal buffer type pin no. pin name signal buffer type b71 d#[2] gtl+ i/o b54 d#[29] gtl+ i/o a72 d#[3] gtl+ i/o a55 d#[30] gtl+ i/o b70 d#[4] gtl+ i/o a53 d#[31] gtl+ i/o a71 d#[5] gtl+ i/o b51 d#[32] gtl+ i/o b68 d#[6] gtl+ i/o a51 d#[33] gtl+ i/o b67 d#[7] gtl+ i/o b48 d#[34] gtl+ i/o a69 d#[8] gtl+ i/o a52 d#[35] gtl+ i/o a68 d#[9] gtl+ i/o b46 d#[36] gtl+ i/o a65 d#[10] gtl+ i/o a49 d#[37] gtl+ i/o a64 d#[11] gtl+ i/o b50 d#[38] gtl+ i/o b66 d#[12] gtl+ i/o a045 d#[39] gtl+ i/o a63 d#[13] gtl+ i/o b47 d#[40] gtl+ i/o a67 d#[14] gtl+ i/o b42 d#[41] gtl+ i/o b64 d#[15] gtl+ i/o a043 d#[42] gtl+ i/o a61 d#[16] gtl+ i/o a48 d#[43] gtl+ i/o b63 d#[17] gtl+ i/o b44 d#[44] gtl+ i/o b60 d#[18] gtl+ i/o a044 d#[45] gtl+ i/o b59 d#[19] gtl+ i/o a039 d#[46] gtl+ i/o b62 d#[20] gtl+ i/o b43 d#[47] gtl+ i/o a60 d#[21] gtl+ i/o b39 d#[48] gtl+ i/o b58 d#[22] gtl+ i/o a040 d#[49] gtl+ i/o a59 d#[23] gtl+ i/o b35 d#[50] gtl+ i/o a57 d#[24] gtl+ i/o a041 d#[51] gtl+ i/o b56 d#[25] gtl+ i/o b40 d#[52] gtl+ i/o b55 d#[26] gtl+ i/o a36 d#[53] gtl+ i/o a56 d#[27] gtl+ i/o b36 d#[54] gtl+ i/o b52 d#[28] gtl+ i/o a33 d#[55] gtl+ i/o
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 70 intel secret (until publication date) table 26. signal listing in order by signal name (contd) pin no. pin name signal buffer type pin no. pin name signal buffer type b34 d#[56] gtl+ i/o a2 gnd v ss a37 d#[57] gtl+ i/o a6 gnd v ss b31 d#[58] gtl+ i/o a10 gnd v ss b38 d#[59] gtl+ i/o a14 gnd v ss a35 d#[60] gtl+ i/o a18 gnd v ss a32 d#[61] gtl+ i/o a22 gnd v ss b30 d#[62] gtl+ i/o a26 gnd v ss b32 d#[63] gtl+ i/o a30 gnd v ss a111 dbsy# gtl+ i/o a34 gnd v ss a105 defer# gtl+ input a38 gnd v ss a25 dep#[0] gtl+ i/o a042 gnd v ss a27 dep#[1] gtl+ i/o a46 gnd v ss b26 dep#[2] gtl+ i/o a50 gnd v ss a28 dep#[3] gtl+ i/o a54 gnd v ss b27 dep#[4] gtl+ i/o a58 gnd v ss a29 dep#[5] gtl+ i/o a62 gnd v ss a31 dep#[6] gtl+ i/o a66 gnd v ss b28 dep#[7] gtl+ i/o a70 gnd v ss b107 drdy# gtl+ i/o a74 gnd v ss b1 emi emi management a78 gnd v ss b41 emi emi management a82 gnd v ss b61 emi emi management a86 gnd v ss b81 emi emi management a90 gnd v ss b100 emi emi management a94 gnd v ss a7 ferr# cmos output a98 gnd v ss b2 flush# cmos input a102 gnd v ss b76 frcerr gtl+ i/o a106 gnd v ss
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 71 intel secret (until publication date) table 26. signal listing in order by signal name (contd) pin no. pin name signal buffer type pin no. pin name signal buffer type a110 gnd v ss b12 reserved reserved for future use a114 gnd v ss b14 reserved reserved for future use a118 gnd v ss b15 reserved reserved for future use b110 hit# gtl+ i/o b20 reserved reserved for future use a109 hitm# gtl+ i/o b112 reserved reserved for future use a4 ierr# cmos output b74 reset# gtl+ input a8 ignne# cmos input b114 rp# gtl+ i/o b4 init# cmos input b108 rs#[0] gtl+ input a17 lint[0]/intr cmos input a112 rs#[1] gtl+ input b16 lint[1]/nmi cmos input b111 rs#[2] gtl+ input b106 lock# gtl+ i/o b115 rsp# gtl+ input b18 picclk apic clock input b101 slotocc# gnd a19 picd[0] cmos i/o b8 slp# cmos input b22 picd[1] cmos i/o b3 smi# cmos input b23 prdy# gtl+ output b6 stpclk# cmos input a20 preq# cmos input b7 tck jtag input a12 pwrgood cmos input a9 tdi jtag input b102 req#[0] gtl+ i/o a11 tdo jtag output b103 req#[1] gtl+ i/o a13 testhi cmos test input a107 req#[2] gtl+ i/o a15 thermtrip# cmos output a108 req#[3] gtl+ i/o b10 tms jtag input b104 req#[4] gtl+ i/o a104 trdy# gtl+ input a16 reserved reserved for future use b11 trst# jtag input a47 reserved reserved for future use b13 vcc_core processor core v cc a88 reserved reserved for future use b17 vcc_core processor core v cc a113 reserved reserved for future use b25 vcc_core processor core v cc a116 reserved reserved for future use b29 vcc_core processor core v cc
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 72 intel secret (until publication date) table 26. signal listing in order by signal name (contd) pin no. pin name signal buffer type pin no. pin name signal buffer type b33 vcc_core processor core v cc b105 vcc_core processor core v cc b37 vcc_core processor core v cc b113 vcc_l2 other v cc b45 vcc_core processor core v cc b117 vcc_l2 other v cc b49 vcc_core processor core v cc b121 vcc_l2 other v cc b53 vcc_core processor core v cc a1 vcc_vtt gtl+ v tt supply b57 vcc_core processor core v cc a3 vcc_vtt gtl+ v tt supply b65 vcc_core processor core v cc b5 vcc_vtt gtl+ v tt supply b69 vcc_core processor core v cc b9 vcc_vtt gtl+ v tt supply b73 vcc_core processor core v cc b109 vcc5 other v cc b77 vcc_core processor core v cc b120 vid[0] vcc core or v ss b85 vcc_core processor core v cc a120 vid[1] vcc core or v ss b89 vcc_core processor core v cc a119 vid[2] vcc core or v ss b93 vcc_core processor core v cc b119 vid[3] vcc core or v ss b97 vcc_core processor core v cc a121 vid[4] vcc core or v ss
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 73 intel secret (until publication date) 6.0. boxed processor specifications 6.1. introduction the pentium ii processor is also offered as an intel boxed processor. intel boxed processors are intended for system integrators who build systems from motherboards and standard components. the boxed pentium ii processor will be supplied with an attached fan/heatsink. this chapter documents motherboard and system r equirements for the fan/heatsink that will be supplied with the boxed pentium ii processor. this chapter is particularly important for oems that manufacture motherboards for system integrators. unless otherwise noted, all figures in this chapter are dimensioned in inches. figure 43 shows a mechanical representation of the boxed pentium ii processor in a retention mechanism. note the airflow of the fan/heatsink is into the center and out of the sides of the fan/heatsink. the large arrows in figure 41 denote the direction of airflow. processor fan shroud covering heatsink fins retention mechanism fan power connector motherboard boxed processor heatsink support mechanism heatsink support mechanism 000904a figure 41. conceptual boxed pentium ? ii processor in retention mechanism
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 74 intel secret (until publication date) 6.2. mechanical specifications this section documents the mechanical specifications of the boxed pentium ii processor fan/heatsink. 6.2.1. boxed processor fan/heatsink dimensions the boxed processor will be shipped with an attached fan/heatsink. clearance is required around the fan/heat sink to ensure unimpeded air flow for proper cooling. the space requirements and dimensions for the boxed processor with integrated fan/heatsink are shown in figure 42 (side view), figure 43 (front view), and figure 44 (top view). all dimensions are in inches. 0.485 (b) 1.291 max (a) slot 1 connecto r fan heatsink s.e.c. cartridge cove r 000890a figure 42. side view space requirements for the boxed processor (fan heatsink supports not shown)
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 75 intel secret (until publication date) 4.90 max (d) 1.25 2.19 (c) power cable connecto r 000891a figure 43. front view space requirements for the boxed processor 0.20 min air space (f) 0.40 min air space (e) (both ends) measure ambient temperature 0.3 above center of fan inlet s.e.c. cartridge cover fan heatsink fan air space 000892 figure 44. top view space requirements for the boxed processor table 27. boxed processor fan/heatsink spatial dimensions fig. ref. label dimensions (inches) min typ max a fan/heatsink depth (off processor thermal plate) 1.291 b fan/heatsink height above motherboard 0.485 c fan/heatsink height (see front view) 2.19 d fan/heatsink width (see front view) 4.90 e airflow keepout zones from end of fan/heatsink 0.40 f airflow keepout zones from face of fan/heatsink 0.20
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 76 intel secret (until publication date) 6.2.2. boxed processor fan/heatsink weight the boxed processor fan/heatsink will not weigh more than 225 grames. see section 4.0 and section 5.0 for details on the processor weight and heatsink requirements. 6.2.3. boxed processor retention mechanism and fan/heatsink support the boxed processor requires a processor retention mechanism as described in ap-588, mechanical and assembly technology for s.e.c. cartridge processors (order number 243333) to secure the processor in slot 1. the boxed processor will not ship with a retention mechanism. motherboards designed for use by system integrators s hould include a retention mechanism and appropriate installation instructions. the boxed processor will ship with its own fan heatsink support. the support differs from supports for passive heatsinks. the boxed processor fan/heatsink support requires heatsink support holes in the motherboard. location and size of these holes are give in figure 45. any motherboard components placed in the area beneath the fan/heatsink supports must recognize the clearance (h) give in table 28 below. component height restrictions for passive heatsink support designs, as described in ap-588, mechanical and assembly technology for s.e.c. cartridge processors (order number 243333), still apply. motherboards designed for use by system integrators should not have objects installed in the heatsink support holes. otherwise, removal instructions for objects pre-installed in the heatsink support holes should be included in the motherboard documentation. table 28. boxed processor fan/heatsink support dimensions 1, 2 fig. ref. label dimensions (inches) min typ max g fan/heatsink support height 2.261 h fan/heatsink support clearance above motherboard 0.430 j fan/heatsink support standoff diameter 0.275 0.300 k fan/heatsink support front edge to heatsink support hole center 0.240 l fan/heatsink support standoff protrusion beneath motherboard 0.06 m motherboard thickness 0.05 0.06 0.075 n spacing between fan/heatsink support posts 4.084 p fan/heatsink support width 0.600 q fan/heatsink support inner edge to heatsink support hole 0.400 notes: 1. this table applies to the dimensions noted in figure 45 through figure 47. 2. all dimensions are in inches. unless otherwise specified, all x.xxx dimension tolerance is 0.005 inches. all x.xx dimension tolerance is 0.01 inches.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 77 intel secret (until publication date) 0.156 thru 0.187 thru 2x recommendations: 0.300 dia. trace keepout --all external layers 0.250 dia. trace keepout --all internal layers a ll dimensions in inches. 1.769 slot 1 connector 1.950 2.932 000875 figure 45. heatsink support hole locations and sizes
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 78 intel secret (until publication date) 2.261 (g) 0.275 dia (j) (0.300 max) 0.240 (k) 1.769 0.060 (l) 0.060 (m) 0.430 (h) 000804 figure 46. side view space requirements for boxed processor fan/heatsink supports
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 79 intel secret (until publication date) 4.084 (n) 0.600 (p) 0.400 (q) 000805 figure 47. top view space requirements for boxed processor fan/heatsink supports 6.3. boxed processor requirements 6.3.1. fan/heatsink power supply the boxed processors fan/heatsink requires a +12 v power supply. a fan power cable will be shipped with the boxed processor to draw power from a power header on the motherboard. the power cable connector and pinout are shown in figure 48. motherboards must provide a matched power header to support the boxed processor. table 29 contains specifications for the input and output signals at the fan/heatsink connector. the cable length will be 7.0 inches (0.25"). the fan/heatsink outputs a sense signal, which is an open-collector output, that pulses at a rate of two pulses per fan revolution. a motherboard pull-up resistor provides v oh to match the motherboard-mounted fan speed monitor requirements, if applicable. use of the sense signal is optional. if the sense signal is not used, pin 3 of the connector should be tied to gnd. the power header on the baseboard must be positioned to allow the fan/heatsink power cable to reach it. the power header identification and location should be documented in the motherboard documentation or on the motherboard. figure 49 shows the recommended location of the fan power connector relative to the slot 1 connector. the motherboard power header should be positioned within 4.75 inches (lateral) of the fan power connector.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 80 intel secret (until publication date) pin signal straight square pin, 3-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pin pitch, 0.025" square pin width. waldom*/molex* p/n 22-01-3037 or equivalent. match with straight pin, friction lock header on motherboard waldom/molex p/n 22-23-2031, amp* p/n 640456-3, or equivalent. 1 2 3 gnd +12v sense 123 000888 figure 48. boxed processor fan/heatsink power cable connector description table 29. fan/heatsink power and signal specifications description min typ max +12 v: 12 volt fan power supply 7 v 12 v 13.8 v ic: fan current draw 100 ma sense: sense frequency (motherboard should pull this pin up to appropriate v cc with resistor) 2 pulses per fan revolution
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 81 intel secret (until publication date) 1.439 1.449 r = 4.75 inches fan power connector location (1.56 inches above motherboard) motherboard fan power header should be positioned within 4.75 inches of fan power connector (lateral distance) slot 1 connector 000913 figure 49. recommended motherboard power header placement relative to fan power connector and slot 1 6.4. thermal specifications this section describes the cooling requirements of the fan/heatsink solution utilized by the boxed processor. 6.4.1. boxed processor cooling requirements the boxed processor will be cooled with a fan/heatsink. the boxed processor fan/heatsink will keep the thermal plate temperature, t plate , within the specifications (see table 20), provided airflow through the fan/heatsink is unimpeded and the air temperature entering the fan is below 45 c (see figure 43 for measurement location). airspace is required around the fan to ensure that the airflow through the fan/heatsink is not blocked. blocking the airflow to the fan/heatsink reduces the cooling efficiency and decreases fan life. figure 44 illustrates an acceptable airspace clearance for the fan/heatsink.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 82 intel secret (until publication date) 7.0. advanced features some nonessential information regarding the pentium ii processor is considered intel confidential and proprietary and is not documented in this publication. this information is available with the appropriate nondisclosure agreements in place. please contact intel corporation for details. this information is specifically targeted at software developers and chipset manufacturers who develop the following types of low-level software and chipsets: operating system kernels virtual memory managers bios and processor test software performance monitoring tools bus cycle information for software developers designing other categories of software, this information does not apply. all of the required program development details are provided in the intel architecture software developers manual: volume 2, instruction set reference (order number 243191), which is publicly available from the intel corporation literature center. to obtain this document, contact the intel corporation literature center at: intel corporation literature center p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 and reference order number 243191
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 83 intel secret (until publication date) appendix a this appendix provides an alphabetical listing of all pentium ii processor signals. the tables at the end of this appendix summarize the signals by direction: output, input, and i/o. a.1 alphabetical signals reference a.1.1 a[35:0]# (i/o) the a[35:3]# (address) signals define a 2 36 -byte physical memory address space. when ads# is active, these pins transmit the address of a transaction; when ads# is inactive, these pins transmit transaction type information. these signals must connect the appropriate pins of all agents on the pentium ii processor system bus. the a[35:24]# signals are parity-protected by the ap1# parity signal, and the a[23:3]# signals are parity-protected by the ap0# parity signal. on the active-to-inactive transition of reset#, the processors sample the a[35:3]# pins to determine their power-on configuration. see the pentium ? ii processor developers manual (order number 243341) for details. a.1.2 a20m# (i) if the a20m# (address-20 mask) input signal is asserted, the pentium ii processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. asserting a20m# emulates the 8086 processors address wrap-around at the 1-mbyte boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. during active reset#, each processor begins sampling the a20m#, ignne# , and lint[1:0] values to determine the ratio of core-clock frequency to bus- clock frequency. (see table 1.) on the active-to- inactive transition of reset#, each processor latches these signals and freezes the frequency ratio internally. system logic must then release these signals for normal operation; see figure 6 for an example implementation of this logic. a.1.3 ads# (i/o) the ads# (address strobe) signal is asserted to indicate the validity of the transaction address on the a[35:3]# pins. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. this signal must connect the appropriate pins on all pentium ii processor system bus agents. a.1.4 aerr# (i/o) the aerr# (address parity error) si gnal is observed and driven by all pentium ii processor system bus agents, and if used, must connect the appropriate pins on all pentium ii processor system bus agents. aerr# observation is optionally enabled during power-on configuration; if enabled, a valid assertion of aerr# aborts the current transaction. if aerr# observation is disabled during power-on configuration, a central agent may handle an assertion of aerr# as appropriate to the machine check architecture (mca) of the system. a.1.5 ap[1:0]# (i/o) the ap[1:0]# (address parity) signals are driven by the request initiator along with ads#, a[35:3]#, req[4:0]#, and rp#. ap1# covers a[35:24]#, and
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 84 intel secret (until publication date) ap0# covers a[23:3]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should connect the appropriate pins of all pentium ii processor system bus agents. a.1.6 bclk (i) the bclk (bus clock) signal determines the bus frequency. all pentium ii processor system bus agents must receive this signal to drive their outputs and latch their inputs on the bclk rising edge. all external timing parameters are specified with respect to the bclk signal. a.1.7 berr# (i/o) the berr# (bus error) si gnal is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all pentium ii processor system bus agents, and must connect the appropriate pins of all such agents, if used. however, pentium ii processors do not observe assertions of the berr# signal. berr# assertion conditions are configurable at a system level. assertion options are defi ned by the following options: enabled or disabled. asserted optionally for internal errors along with ierr#. asserted optionally by the request initiator of a bus transaction after it observes an error. asserted by any bus agent when it observes an error in a bus transaction. a.1.8 binit# (i/o) the binit# (bus initialization) signal may be observed and driven by all pentium ii processor system bus agents, and if used must connect the appropriate pins of all such agents. if the binit# driver is enabled during power on configuration, binit# is asserted to signal any bus condition that prevents reliable future information. if binit# observation is enabled during power-on configuration, and binit# is sampled asserted, all bus state machines are reset and any data which was in transit is lost. all agents reset their rotating id for bus arbitration to the state after reset, and internal count information is lost. the l1 and l2 caches are not affected. if binit# observation is disabled during power-on configuration, a central agent may handle an assertion of binit# as appropriate to the machine check architecture (mca) of the system. a.1.9 bnr# (i/o) the bnr# (block next request) signal is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. since multiple agents might need to request a bus stall at the same time, bnr# is a wire-or signal which must connect the appropriate pins of all pentium ii processor system bus agents. in order to avoid wire-or glitches associated with simultaneous edge transitions driven by multiple drivers, bnr# is activated on specific clock edges and sampled on specific clock edges. a.1.10 bp[3:2]# (i/o) the bp[3:2]# (breakpoint) signals are outputs from the processor that indicate the status of breakpoints. a.1.11 bpm[1:0]# (i/o) the bpm[1:0]# (breakpoint monitor) signals are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. a.1.12 bpri# (i) the bpri# (bus priority request) signal is used to arbitrate for ownership of the pentium ii processor system bus. it must connect the appropriate pins of
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 85 intel secret (until publication date) all pentium ii processor system bus agents. observing bpri# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. a.1.13 br0# (i/o), br1# (i) the br0# and br1# (bus request) pins drive the breq[1:0]# signals in the system. the breq[1:0]# signals are interconnected in a rotating manner to individual processor pins. table 30 gives the rotating interconnect between the processor and bus signals. table 30. br0# (i/o) and br1# signals rotating interconnect bus signal agent 0 pins agent 1 pins breq0# br0# br1# breq1# br1# br0# during power-up configuration, the central agent must assert the br0# bus signal. all symmetric agents sample their br[1:0]# pins on active-to- inactive transition of reset#. the pin on which the agent samples an active level determines its agent id. all agents then configure their pins to match the appropriate bus signal protocol, as shown in table 31. table 31. br[1:0]# signal agent ids pin sampled active in reset# agent id br0# 0 br1# 1 a.1.14 bsel# (i/o) the bsel# (bus select) signal is used for future slot 1 processors and motherboards. this signal must be tied to gnd for proper processor operation. a.1.15 d[63:0]# (i/o) the d[63:0]# (data) signals are the data signals. these signals provide a 64-bit data path between the pentium ii processor system bus agents, and must connect the appropriate pins on all such agents. the data driver asserts drdy# to indicate a valid data transfer. a.1.16 dbsy# (i/o) the dbsy# (data bus busy) si gnal is asserted by the agent responsible for driving data on the pentium ii processor system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on all pentium ii processor system bus agents. a.1.17 defer# (i) the defer# signal is asserted by an agent to indicate that a transaction cannot be guaranteed in- order completion. assertion of defer# is normally the responsibility of the addressed memory or i/o agent. this signal must connect the appropriate pins of all pentium ii processor system bus agents. a.1.18 dep[7:0]# (i/o) the dep[7:0]# (data bus ecc protection) signals provide optional ecc protection for the data bus. they are driven by the agent responsible for driving d[63:0]#, and must connect the appropriate pins of all pentium ii processor system bus agents which use them. the dep[7:0]# signals are enabled or disabled for ecc protection during power on configuration. a.1.19 drdy# (i/o) the drdy# (data r eady) signal is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-cycle data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of all pentium ii processor system bus agents.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 86 intel secret (until publication date) a.1.20 emi emi pins should be connected to motherboard ground and/or to chassis ground through zero ohm (0 w ) resistors. the zero ohm resistors should be placed in close proximity to the slot 1 connector. the path to chassis ground should be short in length and have a low impedance. a.1.21 ferr# (o) the ferr# (floating-point error) si gnal is asserted when the processor detects an unmasked floating- point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using ms-dos*-type floating-point error reporting. a.1.22 flush# (i) when the flush# input signal is asserted, processors write back all data in the modified state from their internal caches and invalidate all internal cache lines. at the completion of this operation, the processor issues a flush acknowledge transaction. the processor does not cache any new data while the flush# signal remains asserted. flush# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. on the active-to-inactive transition of reset#, each processor samples flush# to determine its power- on configuration. see the pentium ? ii processor developers manual (order number 243341) for details. a.1.23 frcerr (i/o) if two processors are configured in a functional redundancy checking (frc) master/checker pair, as a single logical processor, the frcerr (functional redundancy checking error) si gnal is asserted by the checker if a mismatch is detected between the internally sampled outputs and the masters outputs. the checkers frcerr output pin must be connected with the masters frcerr input pin in this configuration. for point-to-point connections, the checker always compares against the masters outputs. for bussed single-driver signals, the checker compares against the signal when the master is the only allowed driver. for bussed multiple-driver wired-or signals, the checker compares against the signal only if the master is expected to drive the signal low. when a processor is configured as an frc checker, frcerr is toggled during its reset action. a checker asserts frcerr for approximately 1 second after the active-to-inactive transition of reset# if it executes its built-in self-test (bist). when bist execution completes, the checker processor deasserts frcerr if bist completed successfully, and continues to assert frcerr if bist fails. if the checker processor does not execute the bist action, then it keeps frcerr asserted for approximately 20 clocks and then deasserts it. all asynchronous signals must be externally synchronized to bclk by system logic during frc mode operation. a.1.24 hit# (i/o), hitm# (i/o) the hit# (snoop hit) and hitm# (hit modified) signals convey transaction snoop operation results, and must connect the appropriate pins of all pentium ii processor system bus agents. any such agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. a.1.25 ierr# (o) the ierr# (internal error) si gnal is asserted by a processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the pentium ii processor system bus. this transaction may optionally be converted to an external error signal (e.g., nmi) by system core logic. the processor will keep ierr# asserted until it is handled in software, or with the assertion of reset#, binit#, or init#.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 87 intel secret (until publication date) a.1.26 ignne# (i) the ignne# (ignore numeric error) si gnal is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating- point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an i/o write instruction, it must be valid along with the trdy# assertion of the corresponding i/o write bus transaction. during active reset#, the pentium ii processor begins sampling the a20m#, ignne#, and lint[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. (see table 1.) on the active- to-inactive transition of reset#, the pentium ii processor latches these signals and freezes the frequency ratio internally. system logic must then release these signals for normal operation; figure 6 for an example implementation of this logic. a.1.27 init# (i) the init# (initialization) signal, when asserted, resets integer registers inside all processors without affecting their internal (l1 or l2) caches or floating- point registers. each processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate pins of all pentium ii processor system bus agents. if init# is sampled active on the active to inactive transition of reset#, t hen the processor executes its built-in self-test (bist). a.1.28 lint[1:0] (i) the lint[1:0] (local apic interrupt) signals must connect the appropriate pins of all apic bus agents, including all processors and the core logic or i/o apic component. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. during active reset#, the pentium ii processor begins sampling the a20m#, ignne#, and lint[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency. (see table 1.) on the active- to-inactive transition of reset#, the pentium ii processor latches these signals and freezes the frequency ratio internally. system logic must then release these signals for normal operation; see figure 6 for an example implementation of this logic. a.1.29 lock# (i/o) the lock# signal indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all pentium ii processor system bus agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the pentium ii processor system bus, it will wait until it observes lock# deasserted. this enables symmetric agents to retain ownership of the pentium ii processor system bus throughout the bus locked operation and ensure the atomicity of lock. a.1.30 picclk (i) the picclk (apic clock) si gnal is an input clock to the processor and core logic or i/o apic which is required for operation of all processors, core logic, and i/o apic components on the apic bus. during frc mode operation, picclk must be ? of (and synchronous to) bclk.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 88 intel secret (until publication date) a.1.31 picd[1:0] (i/o) the picd[1:0] (apic data) si gnals are used for bi- directional serial message passing on the apic bus, and must connect the appropriate pins of all processors and core logic or i/o apic components on the apic bus. a.1.32 pm[1:0]# (o) the pm[1:0]# (performance monitor) signals are outputs from the processor which indicate the status of programmable counters used for monitoring processor performance. a.1.33 prdy# (o) the prdy (probe ready) signal is a processor output used by debug tools to determine processor debug readiness. see the pentium ? ii processor developers manual (order number 243341) for more information on this signal. a.1.34 preq# (i) the preq# (probe request) signal is used by debug tools to request debug operation of the processors. see the pentium ? ii processor developers manual (order number 243341) for more information on this signal. a.1.35 pwrgood (i) the pwrgood (power g ood) signal is a 2.5 v tolerant processor input. the processor requires this signal to be a clean indication that the clo cks and power supplies (vcc core , etc.) are stable and within their specifications. clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high (2.5 v) state. figure 50 illustrates the relationship of pwr good to other system si gnals. pwr good can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. it must also meet the minimum pulse width specification in table 13 and be followed by a 1 ms reset# pulse. the pwrgood si gnal must be supplied to the processor as it is used to protect internal circuits against voltage sequencing issues. the pwr good signal does not need to be synchronized for frc operation. it should be driven high throughout boundary scan operation. a.1.36 req[4:0]# (i/o) the req[4:0]# (request command) signals must connect the appropriate pins of all pentium ii processor system bus agents. they are asserted by the current bus owner over two clock cycles to define the currently active transaction type. a.1.37 reset# (i) asserting the reset# si gnal resets all processors to known states and invalidates their l1 and l2 caches without writing back any of their contents. r eset# must remain active for one microsecond for a warm reset; for a power-on reset, reset# must stay active for at least one millisecond after vcc core and clk have reached their proper specifications. on observing active reset#, all pentium ii processor system bus agents will deassert their outputs within two clocks. a number of bus signals are sampled at the active- to-inactive transition of reset# for power-on configuration. these configuration options are described in the pentium ? ii processor developers manual (order number 243341). the processor may have its outputs tristated via power-on configuration. otherwise, if init# is sampled active during the active-to-inactive transition of reset#, the processor will execute its built-in self-test (bist). whether or not bist is executed, the processor will begin program execution at the reset-vector (default 0_ffff_fff0h). reset# must connect the appropriate pins of all pentium ii processor system bus agents.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 89 12/15/97 5:47 pm 24333502.doc intel confidential (until publication date) bclk pwrgood reset# clock ratio 1 ms v cc l2 v , core cc 000760b figure 50. pwrgood relationship at power-on a.1.38 rp# (i/o) the rp# (request parity) signal is driven by the request initiator, and provides parity protection on ads# and req[4:0]#. it must connect the appropriate pins of all pentium ii processor system bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this definition allows parity to be high when all covered signals are high. a.1.39 rs[2:0]# (i) the rs[2:0]# (response status) signals are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all pentium ii processor system bus agents. a.1.40 rsp# (i) the rsp# (response parity) signal is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. it must connect the appropriate pins of all pentium ii processor system bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. while rs[2:0]# = 000, rsp# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. a.1.41 slotocc# (o) the slotocc# signal is defined to allow a system design to detect the presence of a terminator card or processor in a pentium ii connector. combined with the vid combination of vid[4:0] = 11111 (see section 2.6.), a system can determine if a pentium ii connector is occupied, and whether a processor core is present. see table 32 for states and values for determining the type of package in the slot 1 connector. table 32. slot 1 occupation truth table signal value status slotocc# vid[4:0] 0 anything other than 11111 processor with core in slot 1 connector. slotocc# vid[4:0] 0 11111 terminator cartridge in slot 1 connector (i.e., no core present). slotocc# vid[4:0] 1 any value slot 1 connector not occupied.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 90 12/15/97 5:47 pm 24333502.doc intel confidential (until publication date) a.1.42 slp# (i) the slp# (sleep) signal, when asserted in stop grant state, causes processors to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the phase-locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will recognize only assertions of the slp#, stpclk#, and r eset# signals while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop grant state, restarting its internal clock signals to the bus and apic processor core units. a.1.43 smi# (i) the smi# (system management interrupt) signal is asserted asynchronously by system logic. on accepting a system management interrupt, processors save the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. a.1.44 stpclk# (i) the stpclk# (stop clock) signal, when asserted, causes processors to enter a low power stop grant state. the processor issues a stop grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the bus and apic units. the processor continues to snoop bus transactions and service interrupts while in stop grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. a.1.454 tck (i) the tck (test clock) signal provides the clock input for the pentium ii processor test bus (also known as the test access port). a.1.46 tdi (i) the tdi (test data in) signal transfers serial test data into the pentium ii processor. tdi provides the serial input needed for jtag support. a.1.47 tdo (o) the tdo (test data out) signal transfers serial test data out of the pentium ii processor. tdo provides the serial output needed for jtag support. a.1.48 testhi (i) the testhi signal must be connected to a 2.5 v power source through a 1 C10 k w resistor for proper processor operation. a.1.49 thermtrip# (o) the processor protects itself from catastrophic overheating by use of an internal thermal sensor. this sensor is set well above the normal operating temperature to ensure that there are no false trips. the processor will stop all execution when the junction temperature exceeds approximately 130 c. this is signaled to the system by the thermtrip# (thermal trip) pin. once activated, the signal remains latched, and the processor stopped, until reset# goes active. there is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a reset# pulse will reset the processor and execution will continue. if the temperature has not dropped below the trip level, the processor will continue to drive thermtrip# and remain stopped. a.1.50 tms (i) the tms (test mode select) signal is a jtag support signal used by debug tools. a.1.51 trdy# (i) the trdy# (target ready) signal is asserted by the target to indicate that it is ready to receive a write or implicit write back data transfer. trdy# must connect the appropriate pins of all pentium ii processor system bus agents. a.1.52 trst# (i) the trst# (test reset) signal resets the test access port (tap) logic. trst# must be driven low during power on reset. this can be accomplished with a 680 w pull-down resistor.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 91 12/15/97 5:47 pm 24333502.doc intel confidential (until publication date) a.1.53 vid[4:0] (o) the vid[4:0] (voltage id) pins can be used to support automatic selection of power supply voltages. these pins are not signals, but are either an open circuit or a short circuit to v ss on the processor. the combination of opens and shorts defines the voltage required by the processor. the vid pins are needed to cleanly support voltage specification variations on pentium ii processors. see table 2 for definitions of these pins. the power supply must supply the voltage that is requested by these pins, or disable itself. a.2 signal summaries the following tables list attributes of the pentium ii processor output, input and i/o signals. table 33. output signals 1 name active level clock signal group ferr# low asynch cmos output ierr# low asynch cmos output prdy# low bclk gtl+ output slotocc# low asynch power/other tdo high tck jtag output thermtrip# low asynch cmos output vid[4:0] high asynch power/other note: 1. outputs are not checked in frc mode.
pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz e 92 12/15/97 5:47 pm 24333502.doc intel confidential (until publication date) table 34. input signals 1 name active level clock signal group qualified a20m# low asynch cmos input always 2 bpri# low bclk gtl+ input always br1# low bclk gtl+ input always bclk high clock always defer# low bclk gtl+ input always flush# low asynch cmos input always 2 ignne# low asynch cmos input always 2 init# low asynch cmos input always 2 intr high asynch cmos input apic disabled mode lint[1:0] high asynch cmos input apic enabled mode nmi high asynch cmos input apic disabled mode picclk high apic clock always preq# low asynch cmos input always pwrgood high asynch cmos input always reset# low bclk gtl+ input always rs[2:0]# low bclk gtl+ input always rsp# low bclk gtl+ input always slp# low asynch cmos input during stop grant state smi# low asynch cmos input stpclk# low asynch cmos input tck high jtag input tdi high tck jtag input testhi high asynch power/other always tms high tck jtag input trst# low asynch jtag input trdy# low bclk gtl+ input notes: 1. all asynchronous input signals except pwrgood must be synchronous in frc. 2. synchronous assertion with active tdry# ensures synchronization.
e pentium? ii processor at 233 mhz, 266 mhz, 300 mhz, and 333 mhz 93 12/15/97 5:47 pm 24333502.doc intel confidential (until publication date) table 35. input/output signals (single driver) name active level clock signal group qualified a[35:3]# low bclk gtl+ i/o ads#, ads#+1 ads# low bclk gtl+ i/o always ap[1:0]# low bclk gtl+ i/o ads#, ads#+1 br0# low bclk gtl+ i/o always bp[3:2]# low bclk gtl+ i/o always bpm[1:0]# low bclk gtl+ i/o always bsel# low asynch power/other always d[63:0]# low bclk gtl+ i/o drdy# dbsy# low bclk gtl+ i/o always dep[7:0]# low bclk gtl+ i/o drdy# drdy# low bclk gtl+ i/o always frcerr high bclk gtl+ i/o always lock# low bclk gtl+ i/o always req[4:0]# low bclk gtl+ i/o ads#, ads#+1 rp# low bclk gtl+ i/o ads#, ads#+1 table 36. input/output signals (multiple driver) name active level clock signal group qualified aerr# low bclk gtl+ i/o ads#+3 berr# low bclk gtl+ i/o always bnr# low bclk gtl+ i/o always binit# low bclk gtl+ i/o always hit# low bclk gtl+ i/o always hitm# low bclk gtl+ i/o always picd[1:0] high picclk apic i/o always
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